6b06709221
Copy the support files for the Octeon 1 CPU from sys/mips/octeon1 on the projects/mips side to sys/mips/cavium on the head side to conform to the other vendor code. This code was contributed by Cavium to the project and forward ported by Warner Losh, with some additional code from Randal Stewart. # I'll fix the building problems the move creates in a future commit.
186 lines
5.5 KiB
C
186 lines
5.5 KiB
C
/*------------------------------------------------------------------
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* octeon_fau.h Fetch & Add Unit
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*
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*------------------------------------------------------------------
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*/
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#ifndef ___OCTEON_FAU__H___
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#define ___OCTEON_FAU__H___
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typedef enum {
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OCTEON_FAU_OP_SIZE_8 = 0,
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OCTEON_FAU_OP_SIZE_16 = 1,
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OCTEON_FAU_OP_SIZE_32 = 2,
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OCTEON_FAU_OP_SIZE_64 = 3
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} octeon_fau_op_size_t;
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#define OCTEON_FAU_LOAD_IO_ADDRESS octeon_build_io_address(0x1e, 0)
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#define OCTEON_FAU_BITS_SCRADDR 63,56
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#define OCTEON_FAU_BITS_LEN 55,48
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#define OCTEON_FAU_BITS_INEVAL 35,14
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#define OCTEON_FAU_BITS_TAGWAIT 13,13
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#define OCTEON_FAU_BITS_NOADD 13,13
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#define OCTEON_FAU_BITS_SIZE 12,11
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#define OCTEON_FAU_BITS_REGISTER 10,0
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#define OCTEON_FAU_REG_64_ADDR(x) ((x <<3) + OCTEON_FAU_REG_64_START)
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typedef enum
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{
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OCTEON_FAU_REG_64_START = 0,
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OCTEON_FAU_REG_OQ_ADDR_INDEX = OCTEON_FAU_REG_64_ADDR(0),
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OCTEON_FAU_REG_OQ_ADDR_END = OCTEON_FAU_REG_64_ADDR(31),
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OCTEON_FAU_REG_64_END = OCTEON_FAU_REG_64_ADDR(39),
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} octeon_fau_reg_64_t;
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#define OCTEON_FAU_REG_32_ADDR(x) ((x <<2) + OCTEON_FAU_REG_32_START)
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typedef enum
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{
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OCTEON_FAU_REG_32_START = OCTEON_FAU_REG_64_END,
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OCTEON_FAU_REG_32_END = OCTEON_FAU_REG_32_ADDR(0),
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} octeon_fau_reg_32_t;
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/*
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* octeon_fau_atomic_address
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*
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* Builds a I/O address for accessing the FAU
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*
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* @param tagwait Should the atomic add wait for the current tag switch
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* operation to complete.
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* - 0 = Don't wait
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* - 1 = Wait for tag switch to complete
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* @param reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: When performing 32 and 64 bit access, only the low
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* 22 bits are available.
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* @return Address to read from for atomic update
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*/
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static inline uint64_t octeon_fau_atomic_address (uint64_t tagwait, uint64_t reg,
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int64_t value)
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{
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return (OCTEON_ADD_IO_SEG(OCTEON_FAU_LOAD_IO_ADDRESS) |
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octeon_build_bits(OCTEON_FAU_BITS_INEVAL, value) |
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octeon_build_bits(OCTEON_FAU_BITS_TAGWAIT, tagwait) |
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octeon_build_bits(OCTEON_FAU_BITS_REGISTER, reg));
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}
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/*
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* octeon_fau_store_address
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*
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* Builds a store I/O address for writing to the FAU
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*
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* noadd 0 = Store value is atomically added to the current value
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* 1 = Store value is atomically written over the current value
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* reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* Returns Address to store for atomic update
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*/
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static inline uint64_t octeon_fau_store_address (uint64_t noadd, uint64_t reg)
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{
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return (OCTEON_ADD_IO_SEG(OCTEON_FAU_LOAD_IO_ADDRESS) |
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octeon_build_bits(OCTEON_FAU_BITS_NOADD, noadd) |
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octeon_build_bits(OCTEON_FAU_BITS_REGISTER, reg));
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}
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/*
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* octeon_fau_atomic_add32
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*
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* Perform an atomic 32 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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*/
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static inline void octeon_fau_atomic_add32 (octeon_fau_reg_32_t reg, int32_t value)
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{
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oct_write32(octeon_fau_store_address(0, reg), value);
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}
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/*
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* octeon_fau_fetch_and_add
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*
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* reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 8 for 64 bit access.
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* value Signed value to add.
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* Note: Only the low 22 bits are available.
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* returns Value of the register before the update
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*/
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static inline int64_t octeon_fau_fetch_and_add64 (octeon_fau_reg_64_t reg,
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int64_t val64)
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{
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return (oct_read64(octeon_fau_atomic_address(0, reg, val64)));
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}
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/*
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* octeon_fau_fetch_and_add32
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*
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* reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 8 for 64 bit access.
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* value Signed value to add.
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* Note: Only the low 22 bits are available.
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* returns Value of the register before the update
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*/
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static inline int32_t octeon_fau_fetch_and_add32 (octeon_fau_reg_64_t reg,
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int32_t val32)
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{
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return (oct_read32(octeon_fau_atomic_address(0, reg, val32)));
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}
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/*
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* octeon_fau_atomic_write32
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*
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* Perform an atomic 32 bit write
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*
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* @param reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to write.
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*/
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static inline void octeon_fau_atomic_write32(octeon_fau_reg_32_t reg, int32_t value)
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{
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oct_write32(octeon_fau_store_address(1, reg), value);
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}
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/*
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* octeon_fau_atomic_write64
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*
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* Perform an atomic 32 bit write
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*
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* reg FAU atomic register to access. 0 <= reg < 4096.
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* - Step by 8 for 64 bit access.
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* value Signed value to write.
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*/
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static inline void octeon_fau_atomic_write64 (octeon_fau_reg_64_t reg, int64_t value)
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{
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oct_write64(octeon_fau_store_address(1, reg), value);
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}
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static inline void octeon_fau_atomic_add64 (octeon_fau_reg_64_t reg, int64_t value)
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{
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oct_write64_int64(octeon_fau_store_address(0, reg), value);
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}
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extern void octeon_fau_init(void);
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extern void octeon_fau_enable(void);
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extern void octeon_fau_disable(void);
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#endif /* ___OCTEON_FAU__H___ */
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