6b06709221
Copy the support files for the Octeon 1 CPU from sys/mips/octeon1 on the projects/mips side to sys/mips/cavium on the head side to conform to the other vendor code. This code was contributed by Cavium to the project and forward ported by Warner Losh, with some additional code from Randal Stewart. # I'll fix the building problems the move creates in a future commit.
220 lines
6.3 KiB
C
220 lines
6.3 KiB
C
/*------------------------------------------------------------------
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* octeon_fpa.h Free Pool Allocator
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*
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*------------------------------------------------------------------
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*/
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#ifndef ___OCTEON_FPA__H___
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#define ___OCTEON_FPA__H___
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#define OCTEON_FPA_FPA_OUTPUT_BUFFER_POOL 2 /* Same in octeon_rgmx.h */
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/*
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* OCTEON_FPA_FPF_MARKS = FPA's Queue Free Page FIFO Read Write Marks
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*
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* The high and low watermark register that determines when we write and
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* read free pages from L2C for Queue.
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 42; /* Must be zero */
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uint64_t fpf_wr : 11; /* Write Hi Water mark */
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uint64_t fpf_rd : 11; /* Read Lo Water mark */
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} bits;
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} octeon_fpa_fpf_marks_t;
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/*
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* OCTEON_FPA_CTL_STATUS = FPA's Control/Status Register
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*
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* The FPA's interrupt enable register.
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* - Use with the CVMX_FPA_CTL_STATUS CSR.
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 49; /* Must be zero */
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uint64_t enb : 1; /* Enable */
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uint64_t mem1_err : 7; /* ECC flip 1 */
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uint64_t mem0_err : 7; /* ECC flip 0 */
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} bits;
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} octeon_fpa_ctl_status_t;
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/*
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* OCTEON_FPA_FPF_SIZE = FPA's Queue N Free Page FIFO Size
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*
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* The number of page pointers that will be kept local to the FPA for
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* this Queue. FPA Queues are assigned in order from Queue 0 to
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* Queue 7, though only Queue 0 through Queue x can be used.
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* The sum of the 8 (0-7)OCTEON_FPA_FPF#_SIZE registers must be limited to 2048.
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* - Use with the CVMX_FPA_FPF0_SIZE CSR.
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 52; /* Must be zero */
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/*
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* The number of entries assigned in the FPA FIFO (used to hold
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* page-pointers) for this Queue.
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* The value of this register must divisable by 2, and the FPA will
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* ignore bit [0] of this register.
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* The total of the FPF_SIZ field of the 8 (0-7)OCTEON_FPA_FPF#_MARKS
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* registers must not exceed 2048.
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* After writing this field the FPA will need 10 core clock cycles
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* to be ready for operation. The assignment of location in
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* the FPA FIFO must start with Queue 0, then 1, 2, etc.
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* The number of useable entries will be FPF_SIZ-2.
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*/
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uint64_t fpf_siz : 12;
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} bits;
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} octeon_fpa_fpf_size_t;
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/*
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*OCTEON_FPA_INT_ENB = FPA's Interrupt Enable
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*
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* The FPA's interrupt enable register.
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* - Use with the CVMX_FPA_INT_ENB CSR.
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 60; /* Must be zero */
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uint64_t fed1_dbe : 1; /* Int iff bit3 Int-Sum set */
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uint64_t fed1_sbe : 1; /* Int iff bit2 Int-Sum set */
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uint64_t fed0_dbe : 1; /* Int iff bit1 Int-Sum set */
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uint64_t fed0_sbe : 1; /* Int iff bit0 Int-Sum set */
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} bits;
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} octeon_fpa_int_enb_t;
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/**
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*OCTEON_FPA_INT_SUM = FPA's Interrupt Summary Register
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*
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* Contains the diffrent interrupt summary bits of the FPA.
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* - Use with the CVMX_FPA_INT_SUM CSR.
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 60; /**< Must be zero */
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uint64_t fed1_dbe : 1;
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uint64_t fed1_sbe : 1;
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uint64_t fed0_dbe : 1;
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uint64_t fed0_sbe : 1;
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} bits;
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} octeon_fpa_int_sum_t;
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/*
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*OCTEON_FPA_QUEUE_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register
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*
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* The number of page pointers that are available in the FPA and local DRAM.
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* - Use with the CVMX_FPA_QUEX_AVAILABLE(0..7) CSR.
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 38; /* Must be zero */
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uint64_t queue_size : 26; /* free pages available */
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} bits;
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} octeon_fpa_queue_available_t;
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/*
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*OCTEON_FPA_QUEUE_PAGE_INDEX
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*
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 39; /* Must be zero */
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uint64_t page_index : 25; /* page_index */
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} bits;
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} octeon_fpa_queue_page_index_t;
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#define OCTEON_DID_FPA 5ULL
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#define OCTEON_FPA_POOL_ALIGNMENT (OCTEON_CACHE_LINE_SIZE)
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/*
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* Externs
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*/
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extern void octeon_dump_fpa(void);
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extern void octeon_dump_fpa_pool(u_int pool);
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extern u_int octeon_fpa_pool_size(u_int pool);
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extern void octeon_enable_fpa(void);
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extern void octeon_fpa_fill_pool_mem(u_int pool,
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u_int block_size_words,
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u_int block_num);
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/*
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* octeon_fpa_free
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*
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* Free a mem-block to FPA pool.
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*
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* Takes away this 'buffer' from SW and passes it to FPA for management.
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*
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* pool is FPA pool num, ptr is block ptr, num_cache_lines is number of
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* cache lines to invalidate (not written back).
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*/
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static inline void octeon_fpa_free (void *ptr, u_int pool,
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u_int num_cache_lines)
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{
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octeon_addr_t free_ptr;
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free_ptr.word64 = (uint64_t)OCTEON_PTR2PHYS(ptr);
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free_ptr.sfilldidspace.didspace = OCTEON_ADDR_DIDSPACE(
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OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA, pool));
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/*
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* Do not 'sync'
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* asm volatile ("sync\n");
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*/
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oct_write64(free_ptr.word64, num_cache_lines);
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}
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/*
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* octeon_fpa_alloc
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*
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* Allocate a new block from the FPA
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*
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* Buffer passes away from FPA management to SW control
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*/
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static inline void *octeon_fpa_alloc (u_int pool)
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{
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uint64_t address;
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address = oct_read64(OCTEON_ADDR_DID(OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA,
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pool)));
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if (address) {
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/*
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* 32 bit FPA pointers only
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*/
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/*
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* We only use 32 bit pointers at this time
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*/
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/*XXX mips64 issue */
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return ((void *) MIPS_PHYS_TO_KSEG0(address & 0xffffffff));
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}
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return (NULL);
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}
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static inline uint64_t octeon_fpa_alloc_phys (u_int pool)
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{
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return (oct_read64(OCTEON_ADDR_DID(OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA,
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pool))));
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}
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#endif /* ___OCTEON_FPA__H___ */
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