928e4f221d
calculated at runtime based on how long it takes to set up an event in hardware. This fixes the intermittant 1-minute hang at boot on imx5 systems, and also the occasional oversleeping while running. It doesn't affect imx6 systems, which use different hardware for eventtimers. It turns out that it usually takes about 30 timer ticks to set up the timer compare register, and the old hard-coded minimum period was 10 ticks. On the rare occasions when a timeout event that short was set up, we'd miss the event and have to wait about 64 seconds for counter rollover before the compare interrupt would fire. Instead of just hardcoding a new bigger value, the code now measures the time it takes to do the register read/write sequence to set up the compare register, scales it up by 1.5x to be safe, and calculates the minimum event period from the result. In the real world, the minimum period works out to about 750 nanoseconds on imx5 hardware. |
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allwinner | ||
altera/socfpga | ||
amlogic/aml8726 | ||
annapurna/alpine | ||
arm | ||
at91 | ||
broadcom/bcm2835 | ||
cavium/cns11xx | ||
cloudabi32 | ||
conf | ||
freescale | ||
include | ||
lpc | ||
mv | ||
nvidia | ||
qemu | ||
rockchip | ||
samsung/exynos | ||
ti | ||
versatile | ||
xilinx | ||
xscale |