f17c4e38f5
driver to use it. Add ARM Mali Txxx (Midgard), Gxx (Bifrost) GPU page management code. Sponsored by: UKRI
89 lines
3.5 KiB
C
89 lines
3.5 KiB
C
/*-
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* Copyright (c) 2014 Andrew Turner
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* Copyright (c) 2014-2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM64_IOMMU_IOMMU_PTE_H_
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#define _ARM64_IOMMU_IOMMU_PTE_H_
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/* Level 0 table, 512GiB per entry */
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#define IOMMU_L0_SHIFT 39
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#define IOMMU_L0_SIZE (1ul << IOMMU_L0_SHIFT)
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#define IOMMU_L0_OFFSET (IOMMU_L0_SIZE - 1ul)
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#define IOMMU_L0_INVAL 0x0 /* An invalid address */
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/* 0x1 Level 0 doesn't support block translation */
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/* 0x2 also marks an invalid address */
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#define IOMMU_L0_TABLE 0x3 /* A next-level table */
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/* Level 1 table, 1GiB per entry */
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#define IOMMU_L1_SHIFT 30
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#define IOMMU_L1_SIZE (1 << IOMMU_L1_SHIFT)
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#define IOMMU_L1_OFFSET (IOMMU_L1_SIZE - 1)
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#define IOMMU_L1_INVAL IOMMU_L0_INVAL
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#define IOMMU_L1_BLOCK 0x1
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#define IOMMU_L1_TABLE IOMMU_L0_TABLE
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/* Level 2 table, 2MiB per entry */
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#define IOMMU_L2_SHIFT 21
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#define IOMMU_L2_SIZE (1 << IOMMU_L2_SHIFT)
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#define IOMMU_L2_OFFSET (IOMMU_L2_SIZE - 1)
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#define IOMMU_L2_INVAL IOMMU_L1_INVAL
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#define IOMMU_L2_BLOCK IOMMU_L1_BLOCK
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#define IOMMU_L2_TABLE IOMMU_L1_TABLE
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#define IOMMU_L2_BLOCK_MASK UINT64_C(0xffffffe00000)
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/* Level 3 table, 4KiB per entry */
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#define IOMMU_L3_SHIFT 12
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#define IOMMU_L3_SIZE (1 << IOMMU_L3_SHIFT)
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#define IOMMU_L3_OFFSET (IOMMU_L3_SIZE - 1)
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#define IOMMU_L3_SHIFT 12
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#define IOMMU_L3_INVAL 0x0
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/* 0x1 is reserved */
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/* 0x2 also marks an invalid address */
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#define IOMMU_L3_PAGE 0x3
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#define IOMMU_L3_BLOCK IOMMU_L2_BLOCK /* Mali GPU only. */
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#define IOMMU_L0_ENTRIES_SHIFT 9
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#define IOMMU_L0_ENTRIES (1 << IOMMU_L0_ENTRIES_SHIFT)
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#define IOMMU_L0_ADDR_MASK (IOMMU_L0_ENTRIES - 1)
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#define IOMMU_Ln_ENTRIES_SHIFT 9
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#define IOMMU_Ln_ENTRIES (1 << IOMMU_Ln_ENTRIES_SHIFT)
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#define IOMMU_Ln_ADDR_MASK (IOMMU_Ln_ENTRIES - 1)
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#define IOMMU_Ln_TABLE_MASK ((1 << 12) - 1)
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#define iommu_l0_index(va) (((va) >> IOMMU_L0_SHIFT) & IOMMU_L0_ADDR_MASK)
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#define iommu_l1_index(va) (((va) >> IOMMU_L1_SHIFT) & IOMMU_Ln_ADDR_MASK)
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#define iommu_l2_index(va) (((va) >> IOMMU_L2_SHIFT) & IOMMU_Ln_ADDR_MASK)
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#define iommu_l3_index(va) (((va) >> IOMMU_L3_SHIFT) & IOMMU_Ln_ADDR_MASK)
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#endif /* !_ARM64_IOMMU_IOMMU_PTE_H_ */
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