1038d102c4
This commit adds proper cache and shareability attributes to the TCR register. Set memory attributes to Normal, outer and inner cacheable WBWA. Set shareability to inner and outer shareable when SMP is enabled. Reviewed by: andrew Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3093 |
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arm64 | ||
conf | ||
include |