Zbigniew Bodek 1038d102c4 Set-up proper TCR values for memory related to Translation Table Walking ...

This commit adds proper cache and shareability attributes to
the TCR register.
Set memory attributes to Normal, outer and inner cacheable WBWA.
Set shareability to inner and outer shareable when SMP is enabled.

Reviewed by:   andrew
Obtained from: Semihalf
Sponsored by:  The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3093

2015-07-16 10:22:57 +00:00

..

acpica

Add ARM64TODO comments to ACPI PCI stubs

2015-07-12 18:32:16 +00:00

arm64

Set-up proper TCR values for memory related to Translation Table Walking

2015-07-16 10:22:57 +00:00

conf

Spell crypto correctly.

2015-07-14 10:47:56 +00:00

include

Set-up proper TCR values for memory related to Translation Table Walking

2015-07-16 10:22:57 +00:00