2c66cccab7
the kernel on amd64. Fill and read segment registers for mcontext and signals. Handle traps caused by restoration of the invalidated selectors. Implement user-mode creation and manipulation of the process-specific LDT descriptors for amd64, see sysarch(2). Implement support for TSS i/o port access permission bitmap for amd64. Context-switch LDT and TSS. Do not save and restore segment registers on the context switch, that is handled by kernel enter/leave trampolines now. Remove segment restore code from the signal trampolines for freebsd/amd64, freebsd/ia32 and linux/i386 for the same reason. Implement amd64-specific compat shims for sysarch. Linuxolator (temporary ?) switched to use gsbase for thread_area pointer. TODO: Currently, gdb is not adapted to show segment registers from struct reg. Also, no machine-depended ptrace command is added to set segment registers for debugged process. In collaboration with: pho Discussed with: peter Reviewed by: jhb Linuxolator tested by: dchagin
254 lines
5.6 KiB
ArmAsm
254 lines
5.6 KiB
ArmAsm
/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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/*
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* Interrupt entry points for external interrupts triggered by I/O APICs
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* as well as IPI handlers.
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*/
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#include <machine/asmacros.h>
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#include <machine/apicreg.h>
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#include "assym.s"
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/*
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* I/O Interrupt Entry Point. Rather than having one entry point for
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* each interrupt source, we use one entry point for each 32-bit word
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* in the ISR. The handler determines the highest bit set in the ISR,
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* translates that into a vector, and passes the vector to the
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* lapic_handle_intr() function.
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*/
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#define ISR_VEC(index, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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FAKE_MCOUNT(TF_RIP(%rsp)) ; \
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movq lapic, %rdx ; /* pointer to local APIC */ \
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movl LA_ISR + 16 * (index)(%rdx), %eax ; /* load ISR */ \
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bsrl %eax, %eax ; /* index of highset set bit in ISR */ \
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jz 2f ; \
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addl $(32 * index),%eax ; \
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1: ; \
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movq %rsp, %rsi ; \
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movl %eax, %edi ; /* pass the IRQ */ \
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call lapic_handle_intr ; \
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MEXITCOUNT ; \
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jmp doreti ; \
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2: movl $-1, %eax ; /* send a vector of -1 */ \
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jmp 1b
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(spuriousint)
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/* No EOI cycle used here */
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iretq
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ISR_VEC(1, apic_isr1)
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ISR_VEC(2, apic_isr2)
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ISR_VEC(3, apic_isr3)
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ISR_VEC(4, apic_isr4)
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ISR_VEC(5, apic_isr5)
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ISR_VEC(6, apic_isr6)
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ISR_VEC(7, apic_isr7)
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/*
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* Local APIC periodic timer handler.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(timerint)
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PUSH_FRAME
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FAKE_MCOUNT(TF_RIP(%rsp))
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movq %rsp, %rdi
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call lapic_handle_timer
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MEXITCOUNT
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jmp doreti
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#ifdef SMP
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/*
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* Global address space TLB shootdown.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invltlb)
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pushq %rax
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movq %cr3, %rax /* invalidate the TLB */
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movq %rax, %cr3
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popq %rax
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iretq
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/*
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* Single page TLB shootdown
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invlpg)
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pushq %rax
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movq smp_tlb_addr1, %rax
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invlpg (%rax) /* invalidate single page */
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popq %rax
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iretq
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/*
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* Page range TLB shootdown.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invlrng)
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pushq %rax
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pushq %rdx
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movq smp_tlb_addr1, %rdx
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movq smp_tlb_addr2, %rax
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1: invlpg (%rdx) /* invalidate single page */
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addq $PAGE_SIZE, %rdx
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cmpq %rax, %rdx
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jb 1b
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popq %rdx
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popq %rax
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iretq
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/*
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* Invalidate cache.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(invlcache)
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pushq %rax
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wbinvd
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popq %rax
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iretq
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/*
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* Handler for IPIs sent via the per-cpu IPI bitmap.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(ipi_intr_bitmap_handler)
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PUSH_FRAME
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movq lapic, %rdx
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movl $0, LA_EOI(%rdx) /* End Of Interrupt to APIC */
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FAKE_MCOUNT(TF_RIP(%rsp))
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call ipi_bitmap_handler
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MEXITCOUNT
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jmp doreti
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/*
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* Executed by a CPU when it receives an IPI_STOP from another CPU.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(cpustop)
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PUSH_FRAME
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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call cpustop_handler
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jmp doreti
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/*
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* Executed by a CPU when it receives an IPI_SUSPEND from another CPU.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(cpususpend)
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PUSH_FRAME
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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call cpususpend_handler
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POP_FRAME
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iretq
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/*
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* Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
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*
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* - Calls the generic rendezvous action function.
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*/
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.text
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SUPERALIGN_TEXT
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IDTVEC(rendezvous)
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PUSH_FRAME
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call smp_rendezvous_action
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movq lapic, %rax
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movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
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jmp doreti
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#endif /* SMP */
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