11d47032ee
memory ordering model allows writes to different devices to complete out of order, leading to a situation where the write that clears an interrupt source at a device can complete after a write that unmasks and EOIs the interrupt at the interrupt controller, leading to a spurious re-interrupt. This adds a generic barrier function specific to the needs of interrupt controllers, and calls that function from the GIC and TI AINTC controllers. There may still be other soc-specific controllers that need to make the call. Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com> MFC after: 3 days
187 lines
4.7 KiB
C
187 lines
4.7 KiB
C
/*-
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Based on OMAP3 INTC code by Ben Gray
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define INTC_REVISION 0x00
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#define INTC_SYSCONFIG 0x10
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#define INTC_SYSSTATUS 0x14
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#define INTC_SIR_IRQ 0x40
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#define INTC_CONTROL 0x48
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#define INTC_THRESHOLD 0x68
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#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))
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#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))
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#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))
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#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))
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struct ti_aintc_softc {
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device_t sc_dev;
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struct resource * aintc_res[3];
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bus_space_tag_t aintc_bst;
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bus_space_handle_t aintc_bsh;
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uint8_t ver;
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};
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static struct resource_spec ti_aintc_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ti_aintc_softc *ti_aintc_sc = NULL;
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#define aintc_read_4(reg) \
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bus_space_read_4(ti_aintc_sc->aintc_bst, ti_aintc_sc->aintc_bsh, reg)
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#define aintc_write_4(reg, val) \
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bus_space_write_4(ti_aintc_sc->aintc_bst, ti_aintc_sc->aintc_bsh, reg, val)
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static int
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ti_aintc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ti,aintc"))
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return (ENXIO);
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device_set_desc(dev, "TI AINTC Interrupt Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ti_aintc_attach(device_t dev)
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{
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struct ti_aintc_softc *sc = device_get_softc(dev);
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uint32_t x;
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sc->sc_dev = dev;
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if (ti_aintc_sc)
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return (ENXIO);
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if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]);
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sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]);
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ti_aintc_sc = sc;
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x = aintc_read_4(INTC_REVISION);
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device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF);
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/* SoftReset */
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aintc_write_4(INTC_SYSCONFIG, 2);
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/* Wait for reset to complete */
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while(!(aintc_read_4(INTC_SYSSTATUS) & 1));
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/*Set Priority Threshold */
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aintc_write_4(INTC_THRESHOLD, 0xFF);
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return (0);
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}
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static device_method_t ti_aintc_methods[] = {
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DEVMETHOD(device_probe, ti_aintc_probe),
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DEVMETHOD(device_attach, ti_aintc_attach),
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{ 0, 0 }
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};
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static driver_t ti_aintc_driver = {
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"aintc",
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ti_aintc_methods,
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sizeof(struct ti_aintc_softc),
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};
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static devclass_t ti_aintc_devclass;
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DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 0, 0);
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int
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arm_get_next_irq(int last_irq)
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{
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uint32_t active_irq;
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if (last_irq != -1) {
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aintc_write_4(INTC_ISR_CLEAR(last_irq >> 5),
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1UL << (last_irq & 0x1F));
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aintc_write_4(INTC_CONTROL,1);
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}
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/* Get the next active interrupt */
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active_irq = aintc_read_4(INTC_SIR_IRQ);
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/* Check for spurious interrupt */
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if ((active_irq & 0xffffff80)) {
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device_printf(ti_aintc_sc->sc_dev,
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"Spurious interrupt detected (0x%08x)\n", active_irq);
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aintc_write_4(INTC_SIR_IRQ, 0);
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return -1;
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}
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if (active_irq != last_irq)
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return active_irq;
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else
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return -1;
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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aintc_write_4(INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F)));
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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arm_irq_memory_barrier(nb);
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aintc_write_4(INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));
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}
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