2c478084d6
The new file pci_eb64plus_intr.s deals with the interrupt hardware on the EB64PLUS and was obtained from NetBSD with the NetBSD copyright intact The apecs chipset support code was altered to allow routing interrupts through pci if we're not running on an avanti. Avanti's route all interrupts through isa. Tested by: Wilko Bulte <wilko@yedi.iaf.nl> Partially reviewed by: dfr
576 lines
15 KiB
C
576 lines
15 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: apecs.c,v 1.4 1998/12/04 22:54:42 archie Exp $
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Additional Copyright (c) 1998 by Andrew Gallatin for Duke University
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <alpha/pci/apecsreg.h>
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#include <alpha/pci/apecsvar.h>
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#include <alpha/pci/pcibus.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/swiz.h>
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#include <machine/rpb.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t apecs_devclass;
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static device_t apecs0; /* XXX only one for now */
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static device_t isa0;
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struct apecs_softc {
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vm_offset_t dmem_base; /* dense memory */
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vm_offset_t smem_base; /* sparse memory */
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vm_offset_t io_base; /* dense i/o */
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vm_offset_t cfg0_base; /* dense pci0 config */
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vm_offset_t cfg1_base; /* dense pci1 config */
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};
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#define APECS_SOFTC(dev) (struct apecs_softc*) device_get_softc(dev)
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static alpha_chipset_inb_t apecs_swiz_inb;
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static alpha_chipset_inw_t apecs_swiz_inw;
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static alpha_chipset_inl_t apecs_swiz_inl;
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static alpha_chipset_outb_t apecs_swiz_outb;
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static alpha_chipset_outw_t apecs_swiz_outw;
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static alpha_chipset_outl_t apecs_swiz_outl;
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static alpha_chipset_readb_t apecs_swiz_readb;
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static alpha_chipset_readw_t apecs_swiz_readw;
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static alpha_chipset_readl_t apecs_swiz_readl;
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static alpha_chipset_writeb_t apecs_swiz_writeb;
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static alpha_chipset_writew_t apecs_swiz_writew;
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static alpha_chipset_writel_t apecs_swiz_writel;
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static alpha_chipset_maxdevs_t apecs_swiz_maxdevs;
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static alpha_chipset_cfgreadb_t apecs_swiz_cfgreadb;
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static alpha_chipset_cfgreadw_t apecs_swiz_cfgreadw;
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static alpha_chipset_cfgreadl_t apecs_swiz_cfgreadl;
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static alpha_chipset_cfgwriteb_t apecs_swiz_cfgwriteb;
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static alpha_chipset_cfgwritew_t apecs_swiz_cfgwritew;
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static alpha_chipset_cfgwritel_t apecs_swiz_cfgwritel;
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static alpha_chipset_addrcvt_t apecs_cvt_dense;
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static alpha_chipset_read_hae_t apecs_read_hae;
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static alpha_chipset_write_hae_t apecs_write_hae;
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static alpha_chipset_t apecs_swiz_chipset = {
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apecs_swiz_inb,
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apecs_swiz_inw,
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apecs_swiz_inl,
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apecs_swiz_outb,
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apecs_swiz_outw,
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apecs_swiz_outl,
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apecs_swiz_readb,
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apecs_swiz_readw,
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apecs_swiz_readl,
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apecs_swiz_writeb,
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apecs_swiz_writew,
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apecs_swiz_writel,
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apecs_swiz_maxdevs,
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apecs_swiz_cfgreadb,
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apecs_swiz_cfgreadw,
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apecs_swiz_cfgreadl,
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apecs_swiz_cfgwriteb,
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apecs_swiz_cfgwritew,
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apecs_swiz_cfgwritel,
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apecs_cvt_dense,
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NULL,
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apecs_read_hae,
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apecs_write_hae,
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};
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static int
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apecs_swiz_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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static u_int8_t
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apecs_swiz_inb(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_BYTE(KV(APECS_PCI_SIO), port);
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}
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static u_int16_t
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apecs_swiz_inw(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_WORD(KV(APECS_PCI_SIO), port);
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}
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static u_int32_t
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apecs_swiz_inl(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_LONG(KV(APECS_PCI_SIO), port);
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}
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static void
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apecs_swiz_outb(u_int32_t port, u_int8_t data)
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{
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SPARSE_WRITE_BYTE(KV(APECS_PCI_SIO), port, data);
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alpha_wmb();
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}
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static void
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apecs_swiz_outw(u_int32_t port, u_int16_t data)
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{
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SPARSE_WRITE_WORD(KV(APECS_PCI_SIO), port, data);
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alpha_wmb();
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}
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static void
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apecs_swiz_outl(u_int32_t port, u_int32_t data)
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{
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SPARSE_WRITE_LONG(KV(APECS_PCI_SIO), port, data);
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alpha_wmb();
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}
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/*
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* Memory functions.
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*
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* XXX linux does 32-bit reads/writes via dense space. This doesn't
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* appear to work for devices behind a ppb. I'm using sparse
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* accesses & they appear to work just fine everywhere.
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*/
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static u_int32_t apecs_hae_mem;
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#define REG1 (1UL << 24)
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static __inline void
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apecs_swiz_set_hae_mem(u_int32_t *pa)
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{
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int s;
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u_int32_t msb;
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if(*pa >= REG1){
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msb = *pa & 0xf8000000;
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*pa -= msb;
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s = splhigh();
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if (msb != apecs_hae_mem) {
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apecs_hae_mem = msb;
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REGVAL(EPIC_HAXR1) = apecs_hae_mem;
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alpha_mb();
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apecs_hae_mem = REGVAL(EPIC_HAXR1);
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}
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splx(s);
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}
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}
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static u_int8_t
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apecs_swiz_readb(u_int32_t pa)
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{
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alpha_mb();
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apecs_swiz_set_hae_mem(&pa);
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return SPARSE_READ_BYTE(KV(APECS_PCI_SPARSE), pa);
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}
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static u_int16_t
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apecs_swiz_readw(u_int32_t pa)
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{
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alpha_mb();
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apecs_swiz_set_hae_mem(&pa);
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return SPARSE_READ_WORD(KV(APECS_PCI_SPARSE), pa);
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}
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static u_int32_t
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apecs_swiz_readl(u_int32_t pa)
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{
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alpha_mb();
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apecs_swiz_set_hae_mem(&pa);
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return SPARSE_READ_LONG(KV(APECS_PCI_SPARSE), pa);
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}
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static void
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apecs_swiz_writeb(u_int32_t pa, u_int8_t data)
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{
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apecs_swiz_set_hae_mem(&pa);
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SPARSE_WRITE_BYTE(KV(APECS_PCI_SPARSE), pa, data);
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alpha_wmb();
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}
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static void
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apecs_swiz_writew(u_int32_t pa, u_int16_t data)
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{
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apecs_swiz_set_hae_mem(&pa);
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SPARSE_WRITE_WORD(KV(APECS_PCI_SPARSE), pa, data);
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alpha_wmb();
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}
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static void
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apecs_swiz_writel(u_int32_t pa, u_int32_t data)
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{
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apecs_swiz_set_hae_mem(&pa);
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SPARSE_WRITE_LONG(KV(APECS_PCI_SPARSE), pa, data);
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alpha_wmb();
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}
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#define APECS_SWIZ_CFGOFF(b, s, f, r) \
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(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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#define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) { \
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do { \
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(s) = splhigh(); \
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(old_haxr2) = REGVAL(EPIC_HAXR2); \
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alpha_mb(); \
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REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1; \
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alpha_mb(); \
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} while(0); \
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}
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#define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) { \
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do { \
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alpha_mb(); \
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REGVAL(EPIC_HAXR2) = (old_haxr2); \
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alpha_mb(); \
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splx((s)); \
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} while(0); \
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}
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#define SWIZ_CFGREAD(b, s, f, r, width, type) \
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type val = ~0; \
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int ipl = 0; \
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u_int32_t old_haxr2 = 0; \
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struct apecs_softc* sc = APECS_SOFTC(apecs0); \
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \
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alpha_mb(); \
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APECS_TYPE1_SETUP(b,ipl,old_haxr2); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \
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} \
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APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \
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return val;
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#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \
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int ipl = 0; \
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u_int32_t old_haxr2 = 0; \
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struct apecs_softc* sc = APECS_SOFTC(apecs0); \
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \
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alpha_mb(); \
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APECS_TYPE1_SETUP(b,ipl,old_haxr2); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \
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alpha_wmb(); \
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} \
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APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \
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return;
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#if 1
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static u_int8_t
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apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t);
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}
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static u_int16_t
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apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t);
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}
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static u_int32_t
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apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t);
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}
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static void
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apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t);
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}
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static void
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apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t);
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}
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static void
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apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t);
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}
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#else
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static u_int8_t
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apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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struct apecs_softc* sc = APECS_SOFTC(apecs0);
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return ~0;
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return SPARSE_READ_BYTE(sc->cfg0_base, off);
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}
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static u_int16_t
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apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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struct apecs_softc* sc = APECS_SOFTC(apecs0);
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return ~0;
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return SPARSE_READ_WORD(sc->cfg0_base, off);
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}
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static u_int32_t
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apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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struct apecs_softc* sc = APECS_SOFTC(apecs0);
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
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alpha_mb();
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if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return ~0;
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return SPARSE_READ_LONG(sc->cfg0_base, off);
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}
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static void
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apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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struct apecs_softc* sc = APECS_SOFTC(apecs0);
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
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if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return;
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SPARSE_WRITE_BYTE(sc->cfg0_base, off, data);
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alpha_wmb();
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}
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static void
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apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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struct apecs_softc* sc = APECS_SOFTC(apecs0);
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
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if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return;
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SPARSE_WRITE_WORD(sc->cfg0_base, off, data);
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alpha_wmb();
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}
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static void
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apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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struct apecs_softc* sc = APECS_SOFTC(apecs0);
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vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
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if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return;
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SPARSE_WRITE_LONG(sc->cfg0_base, off, data);
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alpha_wmb();
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}
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#endif
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static vm_offset_t
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apecs_cvt_dense(vm_offset_t addr)
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{
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addr &= 0xffffffffUL;
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return (addr | APECS_PCI_DENSE);
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}
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static u_int64_t
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apecs_read_hae(void)
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{
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return apecs_hae_mem & 0xf8000000;
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}
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static void
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apecs_write_hae(u_int64_t hae)
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{
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u_int32_t pa = hae;
|
|
apecs_swiz_set_hae_mem(&pa);
|
|
}
|
|
|
|
static int apecs_probe(device_t dev);
|
|
static int apecs_attach(device_t dev);
|
|
static int apecs_setup_intr(device_t dev, device_t child, struct resource *irq,
|
|
driver_intr_t *intr, void *arg, void **cookiep);
|
|
static int apecs_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie);
|
|
static device_method_t apecs_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, apecs_probe),
|
|
DEVMETHOD(device_attach, apecs_attach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, pci_release_resource),
|
|
DEVMETHOD(bus_activate_resource, pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, apecs_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, apecs_teardown_intr),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t apecs_driver = {
|
|
"apecs",
|
|
apecs_methods,
|
|
DRIVER_TYPE_MISC,
|
|
sizeof(struct apecs_softc),
|
|
};
|
|
|
|
void
|
|
apecs_init()
|
|
{
|
|
static int initted = 0;
|
|
|
|
if (initted) return;
|
|
initted = 1;
|
|
|
|
if (platform.pci_intr_init)
|
|
platform.pci_intr_init();
|
|
|
|
chipset = apecs_swiz_chipset;
|
|
}
|
|
|
|
static int
|
|
apecs_probe(device_t dev)
|
|
{
|
|
int memwidth;
|
|
if (apecs0)
|
|
return ENXIO;
|
|
apecs0 = dev;
|
|
memwidth = (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64;
|
|
if(memwidth == 64){
|
|
device_set_desc(dev, "DECchip 21071 Core Logic chipset");
|
|
} else {
|
|
device_set_desc(dev, "DECchip 21072 Core Logic chipset");
|
|
}
|
|
apecs_hae_mem = REGVAL(EPIC_HAXR1);
|
|
|
|
pci_init_resources();
|
|
|
|
isa0 = device_add_child(dev, "isa", 0, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
extern void isa_intr(void* frame, u_long vector);
|
|
|
|
static int
|
|
apecs_attach(device_t dev)
|
|
{
|
|
struct apecs_softc* sc = APECS_SOFTC(dev);
|
|
apecs_init();
|
|
|
|
/*
|
|
* the avanti routes interrupts through the isa interrupt
|
|
* controller, so we need to special case it
|
|
*/
|
|
if(hwrpb->rpb_type == ST_DEC_2100_A50)
|
|
chipset.intrdev = isa0;
|
|
else
|
|
chipset.intrdev = apecs0;
|
|
|
|
sc->dmem_base = APECS_PCI_DENSE;
|
|
sc->smem_base = APECS_PCI_SPARSE;
|
|
sc->io_base = APECS_PCI_SIO;
|
|
sc->cfg0_base = KV(APECS_PCI_CONF);
|
|
sc->cfg1_base = NULL;
|
|
|
|
set_iointr(alpha_dispatch_intr);
|
|
|
|
snprintf(chipset_type, sizeof(chipset_type), "apecs");
|
|
chipset_bwx = 0;
|
|
chipset_ports = APECS_PCI_SIO;
|
|
chipset_memory = APECS_PCI_SPARSE;
|
|
chipset_dense = APECS_PCI_DENSE;
|
|
chipset_hae_mask = EPIC_HAXR1_EADDR;
|
|
|
|
bus_generic_attach(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
apecs_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq,
|
|
driver_intr_t *intr, void *arg, void **cookiep)
|
|
{
|
|
int error;
|
|
|
|
error = rman_activate_resource(irq);
|
|
if (error)
|
|
return error;
|
|
|
|
error = alpha_setup_intr(0x900 + (irq->r_start << 4),
|
|
intr, arg, cookiep,
|
|
&intrcnt[INTRCNT_EB64PLUS_IRQ + irq->r_start]);
|
|
if (error)
|
|
return error;
|
|
|
|
/* Enable PCI interrupt */
|
|
platform.pci_intr_enable(irq->r_start);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
apecs_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
alpha_teardown_intr(cookie);
|
|
return rman_deactivate_resource(irq);
|
|
}
|
|
|
|
DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0);
|
|
|