eb69ed7f87
Intel® Arria® 10 SoC. Cadence Quad SPI Flash is not generic SPI controller, but SPI flash controller, so don't use spibus here, instead provide quad spi flash interface. Since it is not on spibus, then mx25l flash device driver is not usable here, so provide new n25q flash device driver with quad spi flash interface. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D10245
77 lines
2.1 KiB
Objective-C
77 lines
2.1 KiB
Objective-C
#-
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# Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
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# All rights reserved.
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#
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# This software was developed by SRI International and the University of
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# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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# ("CTSRD"), as part of the DARPA CRASH research programme.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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# SUCH DAMAGE.
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#
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# $FreeBSD$
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#
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#include <sys/bus.h>
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#include <sys/bio.h>
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INTERFACE qspi;
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METHOD int read {
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device_t dev;
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device_t child;
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struct bio *bp;
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off_t offset;
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caddr_t data;
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off_t count;
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};
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METHOD int write {
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device_t dev;
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device_t child;
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struct bio *bp;
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off_t offset;
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caddr_t data;
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off_t count;
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};
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METHOD int erase {
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device_t dev;
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device_t child;
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off_t offset;
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};
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METHOD int write_reg {
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device_t dev;
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device_t child;
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uint8_t opcode;
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uint8_t *addr;
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uint32_t len;
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};
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METHOD int read_reg {
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device_t dev;
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device_t child;
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uint8_t opcode;
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uint8_t *addr;
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uint32_t len;
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};
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