2de4c7f6d0
Due to the quirky nature of the Synopsys Designware PCIe IP, the type 0 configuration is broadcast and whatever device is plugged into slot, will appear at each 32 device positions of bus0. Mitigate the issue by filtering out duplicated devices on this bus for both DT and ACPI cases. Reviewed by: mw Sponsored by: Semihalf MFC: after 3 weeks Differential revision: https://reviews.freebsd.org/D31887
103 lines
3.2 KiB
C
103 lines
3.2 KiB
C
/*
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* Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* $FreeBSD$
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*
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*/
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#ifndef __PCI_HOST_GENERIC_H_
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#define __PCI_HOST_GENERIC_H_
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#include "pci_if.h"
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/* Assembling ECAM Configuration Address */
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#define PCIE_BUS_SHIFT 20
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#define PCIE_SLOT_SHIFT 15
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#define PCIE_FUNC_SHIFT 12
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#define PCIE_BUS_MASK 0xFF
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#define PCIE_SLOT_MASK 0x1F
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#define PCIE_FUNC_MASK 0x07
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#define PCIE_REG_MASK 0xFFF
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#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
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((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
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(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
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(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
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((reg) & PCIE_REG_MASK))
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#define MAX_RANGES_TUPLES 16
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#define MIN_RANGES_TUPLES 2
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struct pcie_range {
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uint64_t pci_base;
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uint64_t phys_base;
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uint64_t size;
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uint64_t flags;
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#define FLAG_TYPE(x) ((x) & FLAG_TYPE_MASK)
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#define FLAG_TYPE_MASK 0x3
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#define FLAG_TYPE_INVALID 0x0
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#define FLAG_TYPE_IO 0x1
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#define FLAG_TYPE_MEM 0x2
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#define FLAG_TYPE_PMEM 0x3
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};
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struct generic_pcie_core_softc {
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struct pcie_range ranges[MAX_RANGES_TUPLES];
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int nranges;
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int coherent;
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bool has_pmem;
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struct rman pmem_rman;
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struct rman mem_rman;
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struct rman io_rman;
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struct resource *res;
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struct resource *res1;
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int bus_start;
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int bus_end;
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int ecam;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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bus_space_handle_t ioh;
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bus_dma_tag_t dmat;
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uint32_t quirks;
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};
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/* Quirks */
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#define PCIE_ECAM_DESIGNWARE_QUIRK (1 << 0)
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DECLARE_CLASS(generic_pcie_core_driver);
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int pci_host_generic_core_attach(device_t);
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struct resource *pci_host_generic_core_alloc_resource(device_t, device_t, int,
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int *, rman_res_t, rman_res_t, rman_res_t, u_int);
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int pci_host_generic_core_release_resource(device_t, device_t, int, int,
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struct resource *);
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#endif /* __PCI_HOST_GENERIC_H_ */
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