Adrian Chadd 1455de1775 The i8259 controller is initialized incorrectly on MALTA. It writes ...

mask bits to control register and control bits to mask register.

The former causes ICW1_RESET|ICW1_LTIM combination to be written to
control register, which on QEMU results in "level sensitive irq not
supported" error.

Submitted by:	Robert Millan <rmh@debian.org>

2011-07-16 00:30:23 +00:00

..

adm5120

- dump_avail layout should be sequence of [start, end)

2010-12-09 07:47:40 +00:00

alchemy

- dump_avail layout should be sequence of [start, end)

2010-12-09 07:47:40 +00:00

atheros

Remove duplicate header includes

2011-06-26 10:07:48 +00:00

cavium

MFC

2011-06-04 22:05:20 +00:00

compile

…

conf

Include device rt in RT305X config.

2011-07-14 11:53:23 +00:00

idt

- Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP

2011-05-03 19:51:29 +00:00

include

Merge r221846 from largeSMP project branch:

2011-05-23 23:35:50 +00:00

malta

The i8259 controller is initialized incorrectly on MALTA. It writes

2011-07-16 00:30:23 +00:00

mips

MFC

2011-07-04 11:13:00 +00:00

rmi

Remove duplicate header includes

2011-06-26 10:07:48 +00:00

rt305x

Import the initial CPU support for the MIPS RALink RT305x SoC.

2011-04-03 14:39:55 +00:00

sentry5

Remove duplicate header includes

2011-06-26 10:07:48 +00:00

sibyte

Remove duplicate header includes

2011-06-26 10:07:48 +00:00