16263f7a8b
enable flag instead of enable_intr() to restore it to its usual state. getit() is only called from DELAY() so there is no point in optimising its speed (this wasn't so clear when it was extern), and using enable_intr() made it inconvenient to call DELAY() from probes that need to run with interrupts disabled.
847 lines
21 KiB
C
847 lines
21 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.60 1996/06/11 16:11:27 pst Exp $
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*/
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/*
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* inittodr, settodr and support routines written
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* by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
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*
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* reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
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*/
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/*
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* Primitive clock interrupt routines.
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*/
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#include "opt_ddb.h"
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#include "opt_clock.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <machine/clock.h>
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#ifdef CLK_CALIBRATION_LOOP
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#include <machine/cons.h>
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#endif
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <i386/isa/icu.h>
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#include <i386/isa/isa.h>
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#include <i386/isa/isa_device.h>
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#include <i386/isa/rtc.h>
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#include <i386/isa/timerreg.h>
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/*
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* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
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* can use a simple formula for leap years.
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*/
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#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
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#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
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#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
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/*
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* Time in timer cycles that it takes for microtime() to disable interrupts
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* and latch the count. microtime() currently uses "cli; outb ..." so it
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* normally takes less than 2 timer cycles. Add a few for cache misses.
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* Add a few more to allow for latency in bogus calls to microtime() with
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* interrupts already disabled.
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*/
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#define TIMER0_LATCH_COUNT 20
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/*
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* Minimum maximum count that we are willing to program into timer0.
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* Must be large enough to guarantee that the timer interrupt handler
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* returns before the next timer interrupt. Must be larger than
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* TIMER0_LATCH_COUNT so that we don't have to worry about underflow in
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* the calculation of timer0_overflow_threshold.
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*/
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#define TIMER0_MIN_MAX_COUNT TIMER_DIV(20000)
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int adjkerntz; /* local offset from GMT in seconds */
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int disable_rtc_set; /* disable resettodr() if != 0 */
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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u_int idelayed;
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#if defined(I586_CPU) || defined(I686_CPU)
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unsigned i586_ctr_freq;
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unsigned i586_ctr_rate;
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long long i586_ctr_bias;
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long long i586_last_tick;
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unsigned long i586_avg_tick;
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#endif
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int statclock_disable;
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u_int stat_imask = SWI_CLOCK_MASK;
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int timer0_max_count;
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u_int timer0_overflow_threshold;
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u_int timer0_prescaler_count;
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static int beeping = 0;
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static u_int clk_imask = HWI_MASK | SWI_MASK;
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static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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static u_int hardclock_max_count;
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/*
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* XXX new_function and timer_func should not handle clockframes, but
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* timer_func currently needs to hold hardclock to handle the
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* timer0_state == 0 case. We should use register_intr()/unregister_intr()
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* to switch between clkintr() and a slightly different timerintr().
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* This will require locking when acquiring and releasing timer0 - the
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* current (nonexistent) locking doesn't seem to be adequate even now.
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*/
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static void (*new_function) __P((struct clockframe *frame));
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static u_int new_rate;
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static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
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static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
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#ifdef TIMER_FREQ
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static u_int timer_freq = TIMER_FREQ;
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#else
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static u_int timer_freq = 1193182;
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#endif
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static char timer0_state = 0;
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static char timer2_state = 0;
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static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
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#if 0
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void
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clkintr(struct clockframe frame)
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{
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hardclock(&frame);
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setdelayed();
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}
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#else
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static void
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clkintr(struct clockframe frame)
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{
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timer_func(&frame);
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switch (timer0_state) {
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case 0:
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setdelayed();
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break;
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case 1:
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if ((timer0_prescaler_count += timer0_max_count)
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>= hardclock_max_count) {
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hardclock(&frame);
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setdelayed();
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timer0_prescaler_count -= hardclock_max_count;
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}
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break;
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case 2:
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setdelayed();
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timer0_max_count = TIMER_DIV(new_rate);
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timer0_overflow_threshold =
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timer0_max_count - TIMER0_LATCH_COUNT;
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disable_intr();
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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enable_intr();
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timer0_prescaler_count = 0;
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timer_func = new_function;
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timer0_state = 1;
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break;
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case 3:
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if ((timer0_prescaler_count += timer0_max_count)
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>= hardclock_max_count) {
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hardclock(&frame);
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setdelayed();
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timer0_max_count = hardclock_max_count;
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timer0_overflow_threshold =
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timer0_max_count - TIMER0_LATCH_COUNT;
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disable_intr();
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outb(TIMER_MODE,
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TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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enable_intr();
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/*
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* See microtime.s for this magic.
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*/
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time.tv_usec += (27645 *
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(timer0_prescaler_count - hardclock_max_count))
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>> 15;
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if (time.tv_usec >= 1000000)
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time.tv_usec -= 1000000;
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timer0_prescaler_count = 0;
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timer_func = hardclock;;
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timer0_state = 0;
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}
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break;
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}
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}
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#endif
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int
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acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
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{
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if (timer0_state || TIMER_DIV(rate) < TIMER0_MIN_MAX_COUNT ||
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!function)
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return -1;
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new_function = function;
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new_rate = rate;
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timer0_state = 2;
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return 0;
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}
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int
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acquire_timer2(int mode)
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{
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if (timer2_state)
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return -1;
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timer2_state = 1;
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outb(TIMER_MODE, TIMER_SEL2 | (mode &0x3f));
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return 0;
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}
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int
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release_timer0()
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{
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if (!timer0_state)
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return -1;
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timer0_state = 3;
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return 0;
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}
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int
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release_timer2()
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{
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if (!timer2_state)
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return -1;
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timer2_state = 0;
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outb(TIMER_MODE, TIMER_SEL2|TIMER_SQWAVE|TIMER_16BIT);
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return 0;
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}
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/*
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* This routine receives statistical clock interrupts from the RTC.
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* As explained above, these occur at 128 interrupts per second.
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* When profiling, we receive interrupts at a rate of 1024 Hz.
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*
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* This does not actually add as much overhead as it sounds, because
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* when the statistical clock is active, the hardclock driver no longer
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* needs to keep (inaccurate) statistics on its own. This decouples
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* statistics gathering from scheduling interrupts.
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*
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* The RTC chip requires that we read status register C (RTC_INTR)
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* to acknowledge an interrupt, before it will generate the next one.
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*/
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static void
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rtcintr(struct clockframe frame)
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{
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u_char stat;
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stat = rtcin(RTC_INTR);
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if(stat & RTCIR_PERIOD) {
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statclock(&frame);
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}
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}
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#ifdef DDB
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static void
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DDB_printrtc(void)
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{
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printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
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rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
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rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
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rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
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}
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#endif
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static int
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getit(void)
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{
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u_long ef;
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int high, low;
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ef = read_eflags();
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disable_intr();
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/* Select timer0 and latch counter value. */
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outb(TIMER_MODE, TIMER_SEL0);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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write_eflags(ef);
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return ((high << 8) | low);
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}
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/*
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* Wait "n" microseconds.
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* Relies on timer 1 counting down from (timer_freq / hz)
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* Note: timer had better have been programmed before this is first used!
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*/
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void
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DELAY(int n)
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{
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int prev_tick, tick, ticks_left, sec, usec;
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#ifdef DELAYDEBUG
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int getit_calls = 1;
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int n1;
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static int state = 0;
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if (state == 0) {
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state = 1;
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for (n1 = 1; n1 <= 10000000; n1 *= 10)
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DELAY(n1);
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state = 2;
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}
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if (state == 1)
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printf("DELAY(%d)...", n);
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#endif
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/*
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* Read the counter first, so that the rest of the setup overhead is
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* counted. Guess the initial overhead is 20 usec (on most systems it
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* takes about 1.5 usec for each of the i/o's in getit(). The loop
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* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
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* multiplications and divisions to scale the count take a while).
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*/
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prev_tick = getit();
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n -= 20;
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/*
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* Calculate (n * (timer_freq / 1e6)) without using floating point
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* and without any avoidable overflows.
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*/
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sec = n / 1000000;
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usec = n - sec * 1000000;
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ticks_left = sec * timer_freq
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+ usec * (timer_freq / 1000000)
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+ usec * ((timer_freq % 1000000) / 1000) / 1000
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+ usec * (timer_freq % 1000) / 1000000;
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if (n < 0)
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ticks_left = 0; /* XXX timer_freq is unsigned */
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while (ticks_left > 0) {
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tick = getit();
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#ifdef DELAYDEBUG
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++getit_calls;
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#endif
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if (tick > prev_tick)
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ticks_left -= prev_tick - (tick - timer0_max_count);
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else
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ticks_left -= prev_tick - tick;
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prev_tick = tick;
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}
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#ifdef DELAYDEBUG
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if (state == 1)
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printf(" %d calls to getit() at %d usec each\n",
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getit_calls, (n + 5) / getit_calls);
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#endif
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}
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static void
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sysbeepstop(void *chan)
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{
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outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
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release_timer2();
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beeping = 0;
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}
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int
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sysbeep(int pitch, int period)
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{
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if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
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return -1;
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disable_intr();
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outb(TIMER_CNTR2, pitch);
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outb(TIMER_CNTR2, (pitch>>8));
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enable_intr();
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if (!beeping) {
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outb(IO_PPI, inb(IO_PPI) | 3); /* enable counter2 output to speaker */
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beeping = period;
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timeout(sysbeepstop, (void *)NULL, period);
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}
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return 0;
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}
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|
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/*
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* RTC support routines
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*/
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int
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rtcin(reg)
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int reg;
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{
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u_char val;
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outb(IO_RTC, reg);
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inb(0x84);
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val = inb(IO_RTC + 1);
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inb(0x84);
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return (val);
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}
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static __inline void
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writertc(u_char reg, u_char val)
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{
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outb(IO_RTC, reg);
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outb(IO_RTC + 1, val);
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}
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|
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static __inline int
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readrtc(int port)
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{
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return(bcd2bin(rtcin(port)));
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}
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|
|
static u_int
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calibrate_clocks(void)
|
|
{
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u_int count, prev_count, tot_count;
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int sec, start_sec, timeout;
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|
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printf("Calibrating clock(s) relative to mc146818A clock...\n");
|
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if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
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goto fail;
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timeout = 100000000;
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|
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/* Read the mc146818A seconds counter. */
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for (;;) {
|
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if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
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sec = rtcin(RTC_SEC);
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|
break;
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|
}
|
|
if (--timeout == 0)
|
|
goto fail;
|
|
}
|
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|
|
/* Wait for the mC146818A seconds counter to change. */
|
|
start_sec = sec;
|
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for (;;) {
|
|
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
|
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sec = rtcin(RTC_SEC);
|
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if (sec != start_sec)
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break;
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}
|
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if (--timeout == 0)
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goto fail;
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}
|
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|
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/* Start keeping track of the i8254 counter. */
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|
prev_count = getit();
|
|
if (prev_count == 0 || prev_count > timer0_max_count)
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goto fail;
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tot_count = 0;
|
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|
|
#if defined(I586_CPU) || defined(I686_CPU)
|
|
if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)
|
|
wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
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|
#endif
|
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|
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/*
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|
* Wait for the mc146818A seconds counter to change. Read the i8254
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|
* counter for each iteration since this is convenient and only
|
|
* costs a few usec of inaccuracy. The timing of the final reads
|
|
* of the counters almost matches the timing of the initial reads,
|
|
* so the main cause of inaccuracy is the varying latency from
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|
* inside getit() or rtcin(RTC_STATUSA) to the beginning of the
|
|
* rtcin(RTC_SEC) that returns a changed seconds count. The
|
|
* maximum inaccuracy from this cause is < 10 usec on 486's.
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|
*/
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start_sec = sec;
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for (;;) {
|
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if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
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sec = rtcin(RTC_SEC);
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count = getit();
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if (count == 0 || count > timer0_max_count)
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goto fail;
|
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if (count > prev_count)
|
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tot_count += prev_count - (count - timer0_max_count);
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|
else
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tot_count += prev_count - count;
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prev_count = count;
|
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if (sec != start_sec)
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break;
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if (--timeout == 0)
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goto fail;
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}
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|
|
#if defined(I586_CPU) || defined(I686_CPU)
|
|
/*
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|
* Read the cpu cycle counter. The timing considerations are
|
|
* similar to those for the i8254 clock.
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|
*/
|
|
if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) {
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|
unsigned long long i586_count;
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|
|
i586_count = rdtsc();
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i586_ctr_freq = i586_count;
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i586_ctr_rate = (i586_count << I586_CTR_RATE_SHIFT) / 1000000;
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printf("i586 clock: %u Hz, ", i586_ctr_freq);
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|
}
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|
#endif
|
|
|
|
printf("i8254 clock: %u Hz\n", tot_count);
|
|
return (tot_count);
|
|
|
|
fail:
|
|
printf("failed, using default i8254 clock of %u Hz\n", timer_freq);
|
|
return (timer_freq);
|
|
}
|
|
|
|
static void
|
|
set_timer_freq(u_int freq, int intr_freq)
|
|
{
|
|
u_long ef;
|
|
|
|
ef = read_eflags();
|
|
timer_freq = freq;
|
|
timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
|
|
timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT;
|
|
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
|
|
outb(TIMER_CNTR0, timer0_max_count & 0xff);
|
|
outb(TIMER_CNTR0, timer0_max_count >> 8);
|
|
write_eflags(ef);
|
|
}
|
|
|
|
/*
|
|
* Initialize 8253 timer 0 early so that it can be used in DELAY().
|
|
* XXX initialization of other timers is unintentionally left blank.
|
|
*/
|
|
void
|
|
startrtclock()
|
|
{
|
|
u_int delta, freq;
|
|
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
writertc(RTC_STATUSB, RTCSB_24HR);
|
|
|
|
/*
|
|
* Temporarily calibrate with a high intr_freq to get a low
|
|
* timer0_max_count to help detect bogus i8254 counts.
|
|
*/
|
|
set_timer_freq(timer_freq, 20000);
|
|
freq = calibrate_clocks();
|
|
#ifdef CLK_CALIBRATION_LOOP
|
|
if (bootverbose) {
|
|
printf(
|
|
"Press a key on the console to abort clock calibration\n");
|
|
while (!cncheckc())
|
|
calibrate_clocks();
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Use the calibrated i8254 frequency if it seems reasonable.
|
|
* Otherwise use the default, and don't use the calibrated i586
|
|
* frequency.
|
|
*/
|
|
delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
|
|
if (delta < timer_freq / 100) {
|
|
#ifndef CLK_USE_I8254_CALIBRATION
|
|
if (bootverbose)
|
|
printf(
|
|
"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
|
|
freq = timer_freq;
|
|
#endif
|
|
timer_freq = freq;
|
|
} else {
|
|
printf("%d Hz differs from default of %d Hz by more than 1%%\n",
|
|
freq, timer_freq);
|
|
#if defined(I586_CPU) || defined(I686_CPU)
|
|
i586_ctr_freq = 0;
|
|
i586_ctr_rate = 0;
|
|
#endif
|
|
}
|
|
|
|
set_timer_freq(timer_freq, hz);
|
|
|
|
#if defined(I586_CPU) || defined(I686_CPU)
|
|
#ifndef CLK_USE_I586_CALIBRATION
|
|
if (i586_ctr_rate != 0) {
|
|
if (bootverbose)
|
|
printf(
|
|
"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n");
|
|
i586_ctr_freq = 0;
|
|
i586_ctr_rate = 0;
|
|
}
|
|
#endif
|
|
if (i586_ctr_rate == 0 &&
|
|
(cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) {
|
|
/*
|
|
* Calibration of the i586 clock relative to the mc146818A
|
|
* clock failed. Do a less accurate calibration relative
|
|
* to the i8254 clock.
|
|
*/
|
|
unsigned long long i586_count;
|
|
|
|
wrmsr(0x10, 0LL); /* XXX */
|
|
DELAY(1000000);
|
|
i586_count = rdtsc();
|
|
i586_ctr_rate = (i586_count << I586_CTR_RATE_SHIFT) / 1000000;
|
|
#ifdef CLK_USE_I586_CALIBRATION
|
|
printf("i586 clock: %u Hz\n", i586_ctr_freq);
|
|
#endif
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Initialize the time of day register, based on the time base which is, e.g.
|
|
* from a filesystem.
|
|
*/
|
|
void
|
|
inittodr(time_t base)
|
|
{
|
|
unsigned long sec, days;
|
|
int yd;
|
|
int year, month;
|
|
int y, m, s;
|
|
|
|
s = splclock();
|
|
time.tv_sec = base;
|
|
time.tv_usec = 0;
|
|
splx(s);
|
|
|
|
/* Look if we have a RTC present and the time is valid */
|
|
if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
|
|
goto wrong_time;
|
|
|
|
/* wait for time update to complete */
|
|
/* If RTCSA_TUP is zero, we have at least 244us before next update */
|
|
while (rtcin(RTC_STATUSA) & RTCSA_TUP);
|
|
|
|
days = 0;
|
|
#ifdef USE_RTC_CENTURY
|
|
year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
|
|
#else
|
|
year = readrtc(RTC_YEAR) + 1900;
|
|
if (year < 1970)
|
|
year += 100;
|
|
#endif
|
|
if (year < 1970)
|
|
goto wrong_time;
|
|
month = readrtc(RTC_MONTH);
|
|
for (m = 1; m < month; m++)
|
|
days += daysinmonth[m-1];
|
|
if ((month > 2) && LEAPYEAR(year))
|
|
days ++;
|
|
days += readrtc(RTC_DAY) - 1;
|
|
yd = days;
|
|
for (y = 1970; y < year; y++)
|
|
days += DAYSPERYEAR + LEAPYEAR(y);
|
|
sec = ((( days * 24 +
|
|
readrtc(RTC_HRS)) * 60 +
|
|
readrtc(RTC_MIN)) * 60 +
|
|
readrtc(RTC_SEC));
|
|
/* sec now contains the number of seconds, since Jan 1 1970,
|
|
in the local time zone */
|
|
|
|
sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
|
|
|
|
s = splclock();
|
|
time.tv_sec = sec;
|
|
splx(s);
|
|
return;
|
|
|
|
wrong_time:
|
|
printf("Invalid time in real time clock.\n");
|
|
printf("Check and reset the date immediately!\n");
|
|
}
|
|
|
|
/*
|
|
* Write system time back to RTC
|
|
*/
|
|
void
|
|
resettodr()
|
|
{
|
|
unsigned long tm;
|
|
int y, m, s;
|
|
|
|
if (disable_rtc_set)
|
|
return;
|
|
|
|
s = splclock();
|
|
tm = time.tv_sec;
|
|
splx(s);
|
|
|
|
/* Disable RTC updates and interrupts. */
|
|
writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
|
|
|
|
/* Calculate local time to put in RTC */
|
|
|
|
tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
|
|
|
|
writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
|
|
writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
|
|
writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
|
|
|
|
/* We have now the days since 01-01-1970 in tm */
|
|
writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
|
|
for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
|
|
tm >= m;
|
|
y++, m = DAYSPERYEAR + LEAPYEAR(y))
|
|
tm -= m;
|
|
|
|
/* Now we have the years in y and the day-of-the-year in tm */
|
|
writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
|
|
#ifdef USE_RTC_CENTURY
|
|
writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
|
|
#endif
|
|
for (m = 0; ; m++) {
|
|
int ml;
|
|
|
|
ml = daysinmonth[m];
|
|
if (m == 1 && LEAPYEAR(y))
|
|
ml++;
|
|
if (tm < ml)
|
|
break;
|
|
tm -= ml;
|
|
}
|
|
|
|
writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
|
|
writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
|
|
|
|
/* Reenable RTC updates and interrupts. */
|
|
writertc(RTC_STATUSB, rtc_statusb);
|
|
}
|
|
|
|
/*
|
|
* Start both clocks running.
|
|
*/
|
|
void
|
|
cpu_initclocks()
|
|
{
|
|
int diag;
|
|
|
|
if (statclock_disable) {
|
|
/*
|
|
* The stat interrupt mask is different without the
|
|
* statistics clock. Also, don't set the interrupt
|
|
* flag which would normally cause the RTC to generate
|
|
* interrupts.
|
|
*/
|
|
stat_imask = HWI_MASK | SWI_MASK;
|
|
rtc_statusb = RTCSB_24HR;
|
|
} else {
|
|
/* Setting stathz to nonzero early helps avoid races. */
|
|
stathz = RTC_NOPROFRATE;
|
|
profhz = RTC_PROFRATE;
|
|
}
|
|
|
|
/* Finish initializing 8253 timer 0. */
|
|
register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
|
|
/* XXX */ (inthand2_t *)clkintr, &clk_imask,
|
|
/* unit */ 0);
|
|
INTREN(IRQ0);
|
|
#if defined(I586_CPU) || defined(I686_CPU)
|
|
/*
|
|
* Finish setting up anti-jitter measures.
|
|
*/
|
|
if (i586_ctr_rate) {
|
|
i586_last_tick = rdtsc();
|
|
i586_ctr_bias = i586_last_tick;
|
|
}
|
|
#endif
|
|
|
|
/* Initialize RTC. */
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
writertc(RTC_STATUSB, RTCSB_24HR);
|
|
|
|
/* Don't bother enabling the statistics clock. */
|
|
if (statclock_disable)
|
|
return;
|
|
diag = rtcin(RTC_DIAG);
|
|
if (diag != 0)
|
|
printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
|
|
register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0,
|
|
/* XXX */ (inthand2_t *)rtcintr, &stat_imask,
|
|
/* unit */ 0);
|
|
INTREN(IRQ8);
|
|
writertc(RTC_STATUSB, rtc_statusb);
|
|
}
|
|
|
|
void
|
|
setstatclockrate(int newhz)
|
|
{
|
|
if (newhz == RTC_PROFRATE)
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
|
|
else
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
}
|
|
|
|
static int
|
|
sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS
|
|
{
|
|
int error;
|
|
u_int freq;
|
|
|
|
/*
|
|
* Use `i8254' instead of `timer' in external names because `timer'
|
|
* is is too generic. Should use it everywhere.
|
|
*/
|
|
freq = timer_freq;
|
|
error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req);
|
|
if (error == 0 && freq != timer_freq) {
|
|
if (timer0_state != 0)
|
|
return (EBUSY); /* too much trouble to handle */
|
|
set_timer_freq(freq, hz);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
|
|
0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
|
|
|
|
#if defined(I586_CPU) || defined(I686_CPU)
|
|
static int
|
|
sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS
|
|
{
|
|
int error;
|
|
u_int freq;
|
|
|
|
if (i586_ctr_rate == 0)
|
|
return (EOPNOTSUPP);
|
|
freq = i586_ctr_freq;
|
|
error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req);
|
|
if (error == 0 && freq != i586_ctr_freq) {
|
|
i586_ctr_freq = freq;
|
|
i586_ctr_rate = ((unsigned long long)freq <<
|
|
I586_CTR_RATE_SHIFT) / 1000000;
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW,
|
|
0, sizeof(u_int), sysctl_machdep_i586_freq, "I", "");
|
|
#endif /* defined(I586_CPU) || defined(I686_CPU) */
|