8815a86933
It works perfectly on my Compaq Presario M2000Z, but my last attempt on Acer Ferrari 4000 only produce garbled sound. MFC after: 3 days
1091 lines
27 KiB
C
1091 lines
27 KiB
C
/*-
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* Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* FreeBSD pcm driver for ATI IXP 150/200/250/300 AC97 controllers
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*
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* Features
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* * 16bit playback / recording
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* * 32bit native playback - yay!
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*
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* Issues / TODO:
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* * SPDIF
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* * Support for more than 2 channels.
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* * VRA ? VRM ? DRA ?
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* * 32bit native recording (seems broken, disabled)
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*
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*
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* Thanks goes to:
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*
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* Shaharil @ SCAN Associates whom relentlessly providing me the
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* mind blowing Acer Ferrari 4002 WLMi with this ATI IXP hardware.
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*
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* Reinoud Zandijk <reinoud@NetBSD.org> (auixp), which this driver is
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* largely based upon although large part of it has been reworked. His
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* driver is the primary reference and pretty much well documented.
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*
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* Takashi Iwai (ALSA snd-atiixp), for register definitions and some
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* random ninja hackery.
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*/
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pcm/ac97.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <sys/sysctl.h>
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#include <sys/endian.h>
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#include <dev/sound/pci/atiixp.h>
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SND_DECLARE_FILE("$FreeBSD$");
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struct atiixp_dma_op {
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uint32_t addr;
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uint16_t status;
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uint16_t size;
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uint32_t next;
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};
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struct atiixp_info;
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struct atiixp_chinfo {
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct atiixp_info *parent;
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struct atiixp_dma_op *sgd_table;
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bus_addr_t sgd_addr;
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uint32_t enable_bit, flush_bit, linkptr_bit, dma_dt_cur_bit;
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uint32_t dma_segs;
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uint32_t fmt;
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int caps_32bit, dir, active;
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};
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struct atiixp_info {
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device_t dev;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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bus_dma_tag_t parent_dmat;
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bus_dma_tag_t sgd_dmat;
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bus_dmamap_t sgd_dmamap;
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bus_addr_t sgd_addr;
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struct resource *reg, *irq;
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int regtype, regid, irqid;
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void *ih;
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struct ac97_info *codec;
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struct atiixp_chinfo pch;
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struct atiixp_chinfo rch;
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struct atiixp_dma_op *sgd_table;
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struct intr_config_hook delayed_attach;
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uint32_t bufsz;
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uint32_t codec_not_ready_bits, codec_idx, codec_found;
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uint32_t dma_segs;
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int registered_channels;
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struct mtx *lock;
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};
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#define atiixp_rd(_sc, _reg) \
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bus_space_read_4((_sc)->st, (_sc)->sh, _reg)
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#define atiixp_wr(_sc, _reg, _val) \
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bus_space_write_4((_sc)->st, (_sc)->sh, _reg, _val)
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#define atiixp_lock(_sc) snd_mtxlock((_sc)->lock)
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#define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock)
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#define atiixp_assert(_sc) snd_mtxassert((_sc)->lock)
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static uint32_t atiixp_fmt_32bit[] = {
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AFMT_STEREO | AFMT_S16_LE,
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#ifdef AFMT_S32_LE
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AFMT_STEREO | AFMT_S32_LE,
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#endif
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0
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};
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static uint32_t atiixp_fmt[] = {
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static struct pcmchan_caps atiixp_caps_32bit = {
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ATI_IXP_BASE_RATE,
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ATI_IXP_BASE_RATE,
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atiixp_fmt_32bit, 0
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};
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static struct pcmchan_caps atiixp_caps = {
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ATI_IXP_BASE_RATE,
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ATI_IXP_BASE_RATE,
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atiixp_fmt, 0
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};
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static const struct {
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uint16_t vendor;
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uint16_t devid;
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char *desc;
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} atiixp_hw[] = {
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{ ATI_VENDOR_ID, ATI_IXP_200_ID, "ATI IXP 200" },
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{ ATI_VENDOR_ID, ATI_IXP_300_ID, "ATI IXP 300" },
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{ ATI_VENDOR_ID, ATI_IXP_400_ID, "ATI IXP 400" },
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};
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static void atiixp_enable_interrupts(struct atiixp_info *);
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static void atiixp_disable_interrupts(struct atiixp_info *);
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static void atiixp_reset_aclink(struct atiixp_info *);
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static void atiixp_flush_dma(struct atiixp_info *, struct atiixp_chinfo *);
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static void atiixp_enable_dma(struct atiixp_info *, struct atiixp_chinfo *);
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static void atiixp_disable_dma(struct atiixp_info *, struct atiixp_chinfo *);
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static int atiixp_waitready_codec(struct atiixp_info *);
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static int atiixp_rdcd(kobj_t, void *, int);
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static int atiixp_wrcd(kobj_t, void *, int, uint32_t);
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static void *atiixp_chan_init(kobj_t, void *, struct snd_dbuf *,
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struct pcm_channel *, int);
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static int atiixp_chan_setformat(kobj_t, void *, uint32_t);
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static int atiixp_chan_setspeed(kobj_t, void *, uint32_t);
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static int atiixp_chan_setblocksize(kobj_t, void *, uint32_t);
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static void atiixp_buildsgdt(struct atiixp_chinfo *);
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static int atiixp_chan_trigger(kobj_t, void *, int);
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static int atiixp_chan_getptr(kobj_t, void *);
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static struct pcmchan_caps *atiixp_chan_getcaps(kobj_t, void *);
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static void atiixp_intr(void *);
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static void atiixp_dma_cb(void *, bus_dma_segment_t *, int, int);
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static void atiixp_chip_pre_init(struct atiixp_info *);
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static void atiixp_chip_post_init(void *);
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static int atiixp_pci_probe(device_t);
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static int atiixp_pci_attach(device_t);
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static int atiixp_pci_detach(device_t);
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static int atiixp_pci_suspend(device_t);
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static int atiixp_pci_resume(device_t);
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/*
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* ATI IXP helper functions
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*/
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static void
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atiixp_enable_interrupts(struct atiixp_info *sc)
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{
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uint32_t value;
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/* clear all pending */
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atiixp_wr(sc, ATI_REG_ISR, 0xffffffff);
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/* enable all relevant interrupt sources we can handle */
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value = atiixp_rd(sc, ATI_REG_IER);
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value |= ATI_REG_IER_IO_STATUS_EN;
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/*
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* Disable / ignore internal xrun/spdf interrupt flags
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* since it doesn't interest us (for now).
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*/
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#if 0
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value |= ATI_REG_IER_IN_XRUN_EN;
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value |= ATI_REG_IER_OUT_XRUN_EN;
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value |= ATI_REG_IER_SPDF_XRUN_EN;
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value |= ATI_REG_IER_SPDF_STATUS_EN;
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#endif
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atiixp_wr(sc, ATI_REG_IER, value);
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}
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static void
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atiixp_disable_interrupts(struct atiixp_info *sc)
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{
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/* disable all interrupt sources */
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atiixp_wr(sc, ATI_REG_IER, 0);
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/* clear all pending */
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atiixp_wr(sc, ATI_REG_ISR, 0xffffffff);
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}
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static void
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atiixp_reset_aclink(struct atiixp_info *sc)
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{
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uint32_t value, timeout;
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/* if power is down, power it up */
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value = atiixp_rd(sc, ATI_REG_CMD);
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if (value & ATI_REG_CMD_POWERDOWN) {
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/* explicitly enable power */
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value &= ~ATI_REG_CMD_POWERDOWN;
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atiixp_wr(sc, ATI_REG_CMD, value);
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/* have to wait at least 10 usec for it to initialise */
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DELAY(20);
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};
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/* perform a soft reset */
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value = atiixp_rd(sc, ATI_REG_CMD);
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value |= ATI_REG_CMD_AC_SOFT_RESET;
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atiixp_wr(sc, ATI_REG_CMD, value);
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/* need to read the CMD reg and wait aprox. 10 usec to init */
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value = atiixp_rd(sc, ATI_REG_CMD);
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DELAY(20);
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/* clear soft reset flag again */
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value = atiixp_rd(sc, ATI_REG_CMD);
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value &= ~ATI_REG_CMD_AC_SOFT_RESET;
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atiixp_wr(sc, ATI_REG_CMD, value);
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/* check if the ac-link is working; reset device otherwise */
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timeout = 10;
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value = atiixp_rd(sc, ATI_REG_CMD);
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while (!(value & ATI_REG_CMD_ACLINK_ACTIVE)
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&& --timeout) {
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#if 0
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device_printf(sc->dev, "not up; resetting aclink hardware\n");
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#endif
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/* dip aclink reset but keep the acsync */
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value &= ~ATI_REG_CMD_AC_RESET;
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value |= ATI_REG_CMD_AC_SYNC;
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atiixp_wr(sc, ATI_REG_CMD, value);
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/* need to read CMD again and wait again (clocking in issue?) */
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value = atiixp_rd(sc, ATI_REG_CMD);
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DELAY(20);
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/* assert aclink reset again */
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value = atiixp_rd(sc, ATI_REG_CMD);
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value |= ATI_REG_CMD_AC_RESET;
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atiixp_wr(sc, ATI_REG_CMD, value);
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/* check if its active now */
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value = atiixp_rd(sc, ATI_REG_CMD);
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};
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if (timeout == 0)
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device_printf(sc->dev, "giving up aclink reset\n");
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#if 0
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if (timeout != 10)
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device_printf(sc->dev, "aclink hardware reset successful\n");
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#endif
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/* assert reset and sync for safety */
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value = atiixp_rd(sc, ATI_REG_CMD);
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value |= ATI_REG_CMD_AC_SYNC | ATI_REG_CMD_AC_RESET;
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atiixp_wr(sc, ATI_REG_CMD, value);
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}
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static void
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atiixp_flush_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch)
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{
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atiixp_wr(sc, ATI_REG_FIFO_FLUSH, ch->flush_bit);
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}
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static void
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atiixp_enable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch)
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{
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uint32_t value;
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value = atiixp_rd(sc, ATI_REG_CMD);
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if (!(value & ch->enable_bit)) {
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value |= ch->enable_bit;
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atiixp_wr(sc, ATI_REG_CMD, value);
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}
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}
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static void
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atiixp_disable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch)
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{
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uint32_t value;
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value = atiixp_rd(sc, ATI_REG_CMD);
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if (value & ch->enable_bit) {
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value &= ~ch->enable_bit;
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atiixp_wr(sc, ATI_REG_CMD, value);
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}
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}
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/*
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* AC97 interface
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*/
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static int
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atiixp_waitready_codec(struct atiixp_info *sc)
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{
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int timeout = 500;
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do {
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if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) &
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ATI_REG_PHYS_OUT_ADDR_EN) == 0)
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return 0;
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DELAY(1);
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} while (timeout--);
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return -1;
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}
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static int
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atiixp_rdcd(kobj_t obj, void *devinfo, int reg)
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{
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struct atiixp_info *sc = devinfo;
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uint32_t data;
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int timeout;
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if (atiixp_waitready_codec(sc))
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return -1;
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data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
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ATI_REG_PHYS_OUT_ADDR_EN |
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ATI_REG_PHYS_OUT_RW | sc->codec_idx;
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atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data);
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if (atiixp_waitready_codec(sc))
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return -1;
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timeout = 500;
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do {
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data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR);
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if (data & ATI_REG_PHYS_IN_READ_FLAG)
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return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
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DELAY(1);
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} while (timeout--);
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if (reg < 0x7c)
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device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg);
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return -1;
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}
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static int
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atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data)
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{
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struct atiixp_info *sc = devinfo;
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if (atiixp_waitready_codec(sc))
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return -1;
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data = (data << ATI_REG_PHYS_OUT_DATA_SHIFT) |
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(((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
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ATI_REG_PHYS_OUT_ADDR_EN | sc->codec_idx;
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atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data);
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return 0;
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}
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static kobj_method_t atiixp_ac97_methods[] = {
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KOBJMETHOD(ac97_read, atiixp_rdcd),
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KOBJMETHOD(ac97_write, atiixp_wrcd),
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{ 0, 0 }
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};
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AC97_DECLARE(atiixp_ac97);
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/*
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* Playback / Record channel interface
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*/
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static void *
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atiixp_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
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struct pcm_channel *c, int dir)
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{
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struct atiixp_info *sc = devinfo;
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struct atiixp_chinfo *ch;
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int num;
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atiixp_lock(sc);
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if (dir == PCMDIR_PLAY) {
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ch = &sc->pch;
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ch->linkptr_bit = ATI_REG_OUT_DMA_LINKPTR;
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ch->enable_bit = ATI_REG_CMD_OUT_DMA_EN | ATI_REG_CMD_SEND_EN;
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ch->flush_bit = ATI_REG_FIFO_OUT_FLUSH;
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ch->dma_dt_cur_bit = ATI_REG_OUT_DMA_DT_CUR;
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/* Native 32bit playback working properly */
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ch->caps_32bit = 1;
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} else {
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ch = &sc->rch;
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ch->linkptr_bit = ATI_REG_IN_DMA_LINKPTR;
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ch->enable_bit = ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_RECEIVE_EN;
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ch->flush_bit = ATI_REG_FIFO_IN_FLUSH;
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ch->dma_dt_cur_bit = ATI_REG_IN_DMA_DT_CUR;
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/* XXX Native 32bit recording appear to be broken */
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ch->caps_32bit = 1;
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}
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ch->buffer = b;
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ch->parent = sc;
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ch->channel = c;
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ch->dir = dir;
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ch->dma_segs = sc->dma_segs;
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atiixp_unlock(sc);
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if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1)
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return NULL;
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atiixp_lock(sc);
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num = sc->registered_channels++;
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ch->sgd_table = &sc->sgd_table[num * ch->dma_segs];
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ch->sgd_addr = sc->sgd_addr +
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(num * ch->dma_segs * sizeof(struct atiixp_dma_op));
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atiixp_disable_dma(sc, ch);
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atiixp_unlock(sc);
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return ch;
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}
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static int
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atiixp_chan_setformat(kobj_t obj, void *data, uint32_t format)
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{
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struct atiixp_chinfo *ch = data;
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struct atiixp_info *sc = ch->parent;
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uint32_t value;
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atiixp_lock(sc);
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if (ch->dir == PCMDIR_REC) {
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value = atiixp_rd(sc, ATI_REG_CMD);
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value &= ~ATI_REG_CMD_INTERLEAVE_IN;
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if (ch->caps_32bit == 0 ||
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(format & (AFMT_8BIT|AFMT_16BIT)) != 0)
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value |= ATI_REG_CMD_INTERLEAVE_IN;
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atiixp_wr(sc, ATI_REG_CMD, value);
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} else {
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value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT);
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value &= ~ATI_REG_OUT_DMA_SLOT_MASK;
|
|
/* We do not have support for more than 2 channels, _yet_. */
|
|
value |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
|
|
ATI_REG_OUT_DMA_SLOT_BIT(4);
|
|
value |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
|
|
atiixp_wr(sc, ATI_REG_OUT_DMA_SLOT, value);
|
|
value = atiixp_rd(sc, ATI_REG_CMD);
|
|
value &= ~ATI_REG_CMD_INTERLEAVE_OUT;
|
|
if (ch->caps_32bit == 0 ||
|
|
(format & (AFMT_8BIT|AFMT_16BIT)) != 0)
|
|
value |= ATI_REG_CMD_INTERLEAVE_OUT;
|
|
atiixp_wr(sc, ATI_REG_CMD, value);
|
|
value = atiixp_rd(sc, ATI_REG_6CH_REORDER);
|
|
value &= ~ATI_REG_6CH_REORDER_EN;
|
|
atiixp_wr(sc, ATI_REG_6CH_REORDER, value);
|
|
}
|
|
ch->fmt = format;
|
|
atiixp_unlock(sc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
atiixp_chan_setspeed(kobj_t obj, void *data, uint32_t spd)
|
|
{
|
|
/* XXX We're supposed to do VRA/DRA processing right here */
|
|
return ATI_IXP_BASE_RATE;
|
|
}
|
|
|
|
static int
|
|
atiixp_chan_setblocksize(kobj_t obj, void *data, uint32_t blksz)
|
|
{
|
|
struct atiixp_chinfo *ch = data;
|
|
struct atiixp_info *sc = ch->parent;
|
|
|
|
if (blksz > (sc->bufsz / ch->dma_segs))
|
|
blksz = sc->bufsz / ch->dma_segs;
|
|
|
|
sndbuf_resize(ch->buffer, ch->dma_segs, blksz);
|
|
|
|
return sndbuf_getblksz(ch->buffer);
|
|
}
|
|
|
|
static void
|
|
atiixp_buildsgdt(struct atiixp_chinfo *ch)
|
|
{
|
|
uint32_t addr, blksz;
|
|
int i;
|
|
|
|
addr = sndbuf_getbufaddr(ch->buffer);
|
|
blksz = sndbuf_getblksz(ch->buffer);
|
|
|
|
for (i = 0; i < ch->dma_segs; i++) {
|
|
ch->sgd_table[i].addr = htole32(addr + (i * blksz));
|
|
ch->sgd_table[i].status = htole16(0);
|
|
ch->sgd_table[i].size = htole16(blksz >> 2);
|
|
ch->sgd_table[i].next = htole32((uint32_t)ch->sgd_addr +
|
|
(((i + 1) % ch->dma_segs) *
|
|
sizeof(struct atiixp_dma_op)));
|
|
}
|
|
}
|
|
|
|
static int
|
|
atiixp_chan_trigger(kobj_t obj, void *data, int go)
|
|
{
|
|
struct atiixp_chinfo *ch = data;
|
|
struct atiixp_info *sc = ch->parent;
|
|
uint32_t value;
|
|
|
|
atiixp_lock(sc);
|
|
|
|
switch (go) {
|
|
case PCMTRIG_START:
|
|
atiixp_flush_dma(sc, ch);
|
|
atiixp_buildsgdt(ch);
|
|
atiixp_wr(sc, ch->linkptr_bit, 0);
|
|
atiixp_enable_dma(sc, ch);
|
|
atiixp_wr(sc, ch->linkptr_bit,
|
|
(uint32_t)ch->sgd_addr | ATI_REG_LINKPTR_EN);
|
|
break;
|
|
case PCMTRIG_STOP:
|
|
case PCMTRIG_ABORT:
|
|
atiixp_disable_dma(sc, ch);
|
|
atiixp_flush_dma(sc, ch);
|
|
break;
|
|
default:
|
|
atiixp_unlock(sc);
|
|
return 0;
|
|
break;
|
|
}
|
|
|
|
/* Update bus busy status */
|
|
value = atiixp_rd(sc, ATI_REG_IER);
|
|
if (atiixp_rd(sc, ATI_REG_CMD) & (
|
|
ATI_REG_CMD_SEND_EN | ATI_REG_CMD_RECEIVE_EN |
|
|
ATI_REG_CMD_SPDF_OUT_EN))
|
|
value |= ATI_REG_IER_SET_BUS_BUSY;
|
|
else
|
|
value &= ~ATI_REG_IER_SET_BUS_BUSY;
|
|
atiixp_wr(sc, ATI_REG_IER, value);
|
|
|
|
atiixp_unlock(sc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
atiixp_chan_getptr(kobj_t obj, void *data)
|
|
{
|
|
struct atiixp_chinfo *ch = data;
|
|
struct atiixp_info *sc = ch->parent;
|
|
uint32_t ptr;
|
|
|
|
atiixp_lock(sc);
|
|
ptr = atiixp_rd(sc, ch->dma_dt_cur_bit);
|
|
atiixp_unlock(sc);
|
|
|
|
return ptr;
|
|
}
|
|
|
|
static struct pcmchan_caps *
|
|
atiixp_chan_getcaps(kobj_t obj, void *data)
|
|
{
|
|
struct atiixp_chinfo *ch = data;
|
|
|
|
if (ch->caps_32bit)
|
|
return &atiixp_caps_32bit;
|
|
return &atiixp_caps;
|
|
}
|
|
|
|
static kobj_method_t atiixp_chan_methods[] = {
|
|
KOBJMETHOD(channel_init, atiixp_chan_init),
|
|
KOBJMETHOD(channel_setformat, atiixp_chan_setformat),
|
|
KOBJMETHOD(channel_setspeed, atiixp_chan_setspeed),
|
|
KOBJMETHOD(channel_setblocksize, atiixp_chan_setblocksize),
|
|
KOBJMETHOD(channel_trigger, atiixp_chan_trigger),
|
|
KOBJMETHOD(channel_getptr, atiixp_chan_getptr),
|
|
KOBJMETHOD(channel_getcaps, atiixp_chan_getcaps),
|
|
{ 0, 0 }
|
|
};
|
|
CHANNEL_DECLARE(atiixp_chan);
|
|
|
|
/*
|
|
* PCI driver interface
|
|
*/
|
|
static void
|
|
atiixp_intr(void *p)
|
|
{
|
|
struct atiixp_info *sc = p;
|
|
uint32_t status, enable, detected_codecs;
|
|
|
|
atiixp_lock(sc);
|
|
status = atiixp_rd(sc, ATI_REG_ISR);
|
|
|
|
if (status == 0) {
|
|
atiixp_unlock(sc);
|
|
return;
|
|
}
|
|
|
|
if ((status & ATI_REG_ISR_IN_STATUS) && sc->rch.channel) {
|
|
atiixp_unlock(sc);
|
|
chn_intr(sc->rch.channel);
|
|
atiixp_lock(sc);
|
|
}
|
|
if ((status & ATI_REG_ISR_OUT_STATUS) && sc->pch.channel) {
|
|
atiixp_unlock(sc);
|
|
chn_intr(sc->pch.channel);
|
|
atiixp_lock(sc);
|
|
}
|
|
|
|
#if 0
|
|
if (status & ATI_REG_ISR_IN_XRUN) {
|
|
device_printf(sc->dev,
|
|
"Recieve IN XRUN interrupt\n");
|
|
}
|
|
if (status & ATI_REG_ISR_OUT_XRUN) {
|
|
device_printf(sc->dev,
|
|
"Recieve OUT XRUN interrupt\n");
|
|
}
|
|
#endif
|
|
|
|
if (status & CODEC_CHECK_BITS) {
|
|
/* mark missing codecs as not ready */
|
|
detected_codecs = status & CODEC_CHECK_BITS;
|
|
sc->codec_not_ready_bits |= detected_codecs;
|
|
|
|
/* disable detected interupt sources */
|
|
enable = atiixp_rd(sc, ATI_REG_IER);
|
|
enable &= ~detected_codecs;
|
|
atiixp_wr(sc, ATI_REG_IER, enable);
|
|
}
|
|
|
|
/* acknowledge */
|
|
atiixp_wr(sc, ATI_REG_ISR, status);
|
|
atiixp_unlock(sc);
|
|
}
|
|
|
|
static void
|
|
atiixp_dma_cb(void *p, bus_dma_segment_t *bds, int a, int b)
|
|
{
|
|
struct atiixp_info *sc = (struct atiixp_info *)p;
|
|
sc->sgd_addr = bds->ds_addr;
|
|
}
|
|
|
|
static void
|
|
atiixp_chip_pre_init(struct atiixp_info *sc)
|
|
{
|
|
uint32_t value;
|
|
|
|
atiixp_lock(sc);
|
|
|
|
/* disable interrupts */
|
|
atiixp_disable_interrupts(sc);
|
|
|
|
/* clear all DMA enables (preserving rest of settings) */
|
|
value = atiixp_rd(sc, ATI_REG_CMD);
|
|
value &= ~(ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_OUT_DMA_EN |
|
|
ATI_REG_CMD_SPDF_OUT_EN );
|
|
atiixp_wr(sc, ATI_REG_CMD, value);
|
|
|
|
/* reset aclink */
|
|
atiixp_reset_aclink(sc);
|
|
|
|
sc->codec_not_ready_bits = 0;
|
|
|
|
/* enable all codecs to interrupt as well as the new frame interrupt */
|
|
atiixp_wr(sc, ATI_REG_IER, CODEC_CHECK_BITS);
|
|
|
|
atiixp_unlock(sc);
|
|
}
|
|
|
|
static void
|
|
atiixp_chip_post_init(void *arg)
|
|
{
|
|
struct atiixp_info *sc = (struct atiixp_info *)arg;
|
|
int i, timeout, found;
|
|
char status[SND_STATUSLEN];
|
|
|
|
atiixp_lock(sc);
|
|
|
|
if (sc->delayed_attach.ich_func) {
|
|
config_intrhook_disestablish(&sc->delayed_attach);
|
|
sc->delayed_attach.ich_func = NULL;
|
|
}
|
|
|
|
/* wait for the interrupts to happen */
|
|
timeout = 100; /* 100.000 usec -> 0.1 sec */
|
|
|
|
while (--timeout) {
|
|
atiixp_unlock(sc);
|
|
DELAY(1000);
|
|
atiixp_lock(sc);
|
|
if (sc->codec_not_ready_bits)
|
|
break;
|
|
}
|
|
|
|
atiixp_disable_interrupts(sc);
|
|
|
|
if (timeout == 0) {
|
|
device_printf(sc->dev,
|
|
"WARNING: timeout during codec detection; "
|
|
"codecs might be present but haven't interrupted\n");
|
|
atiixp_unlock(sc);
|
|
return;
|
|
}
|
|
|
|
found = 0;
|
|
|
|
/*
|
|
* ATI IXP can have upto 3 codecs, but single codec should be
|
|
* suffice for now.
|
|
*/
|
|
if (!(sc->codec_not_ready_bits &
|
|
ATI_REG_ISR_CODEC0_NOT_READY)) {
|
|
/* codec 0 present */
|
|
sc->codec_found++;
|
|
sc->codec_idx = 0;
|
|
found++;
|
|
}
|
|
|
|
if (!(sc->codec_not_ready_bits &
|
|
ATI_REG_ISR_CODEC1_NOT_READY)) {
|
|
/* codec 1 present */
|
|
sc->codec_found++;
|
|
}
|
|
|
|
if (!(sc->codec_not_ready_bits &
|
|
ATI_REG_ISR_CODEC2_NOT_READY)) {
|
|
/* codec 2 present */
|
|
sc->codec_found++;
|
|
}
|
|
|
|
atiixp_unlock(sc);
|
|
|
|
if (found == 0)
|
|
return;
|
|
|
|
/* create/init mixer */
|
|
sc->codec = AC97_CREATE(sc->dev, sc, atiixp_ac97);
|
|
if (sc->codec == NULL)
|
|
goto postinitbad;
|
|
|
|
mixer_init(sc->dev, ac97_getmixerclass(), sc->codec);
|
|
|
|
if (pcm_register(sc->dev, sc, ATI_IXP_NPCHAN, ATI_IXP_NRCHAN))
|
|
goto postinitbad;
|
|
|
|
for (i = 0; i < ATI_IXP_NPCHAN; i++)
|
|
pcm_addchan(sc->dev, PCMDIR_PLAY, &atiixp_chan_class, sc);
|
|
for (i = 0; i < ATI_IXP_NRCHAN; i++)
|
|
pcm_addchan(sc->dev, PCMDIR_REC, &atiixp_chan_class, sc);
|
|
|
|
snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s",
|
|
rman_get_start(sc->reg), rman_get_start(sc->irq),
|
|
PCM_KLDSTRING(snd_atiixp));
|
|
|
|
pcm_setstatus(sc->dev, status);
|
|
|
|
atiixp_lock(sc);
|
|
atiixp_enable_interrupts(sc);
|
|
atiixp_unlock(sc);
|
|
|
|
return;
|
|
|
|
postinitbad:
|
|
if (sc->codec)
|
|
ac97_destroy(sc->codec);
|
|
if (sc->ih)
|
|
bus_teardown_intr(sc->dev, sc->irq, sc->ih);
|
|
if (sc->reg)
|
|
bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg);
|
|
if (sc->irq)
|
|
bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
if (sc->parent_dmat)
|
|
bus_dma_tag_destroy(sc->parent_dmat);
|
|
if (sc->sgd_dmamap)
|
|
bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap);
|
|
if (sc->sgd_dmat)
|
|
bus_dma_tag_destroy(sc->sgd_dmat);
|
|
if (sc->lock)
|
|
snd_mtxfree(sc->lock);
|
|
free(sc, M_DEVBUF);
|
|
}
|
|
|
|
static int
|
|
atiixp_pci_probe(device_t dev)
|
|
{
|
|
int i;
|
|
uint16_t devid, vendor;
|
|
|
|
vendor = pci_get_vendor(dev);
|
|
devid = pci_get_device(dev);
|
|
for (i = 0; i < sizeof(atiixp_hw)/sizeof(atiixp_hw[0]); i++) {
|
|
if (vendor == atiixp_hw[i].vendor &&
|
|
devid == atiixp_hw[i].devid) {
|
|
device_set_desc(dev, atiixp_hw[i].desc);
|
|
return BUS_PROBE_DEFAULT;
|
|
}
|
|
}
|
|
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
atiixp_pci_attach(device_t dev)
|
|
{
|
|
struct atiixp_info *sc;
|
|
int i;
|
|
|
|
if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
|
|
device_printf(dev, "cannot allocate softc\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
|
|
sc->dev = dev;
|
|
/*
|
|
* Default DMA segments per playback / recording channel
|
|
*/
|
|
sc->dma_segs = ATI_IXP_DMA_CHSEGS;
|
|
|
|
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
|
pci_enable_busmaster(dev);
|
|
|
|
sc->regid = PCIR_BAR(0);
|
|
sc->regtype = SYS_RES_MEMORY;
|
|
sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
|
|
RF_ACTIVE);
|
|
|
|
if (!sc->reg) {
|
|
device_printf(dev, "unable to allocate register space\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->st = rman_get_bustag(sc->reg);
|
|
sc->sh = rman_get_bushandle(sc->reg);
|
|
|
|
sc->bufsz = pcm_getbuffersize(dev, 4096, ATI_IXP_DEFAULT_BUFSZ, 65536);
|
|
|
|
sc->irqid = 0;
|
|
sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
if (!sc->irq ||
|
|
snd_setup_intr(dev, sc->irq, INTR_MPSAFE,
|
|
atiixp_intr, sc, &sc->ih)) {
|
|
device_printf(dev, "unable to map interrupt\n");
|
|
goto bad;
|
|
}
|
|
|
|
/*
|
|
* Let the user choose the best DMA segments.
|
|
*/
|
|
if (resource_int_value(device_get_name(dev),
|
|
device_get_unit(dev), "dma_segs",
|
|
&i) == 0) {
|
|
if (i < ATI_IXP_DMA_CHSEGS_MIN)
|
|
i = ATI_IXP_DMA_CHSEGS_MIN;
|
|
if (i > ATI_IXP_DMA_CHSEGS_MAX)
|
|
i = ATI_IXP_DMA_CHSEGS_MAX;
|
|
/* round the value */
|
|
sc->dma_segs = i & ~1;
|
|
}
|
|
|
|
/*
|
|
* DMA tag for scatter-gather buffers and link pointers
|
|
*/
|
|
if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
|
|
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
|
/*highaddr*/BUS_SPACE_MAXADDR,
|
|
/*filter*/NULL, /*filterarg*/NULL,
|
|
/*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
|
|
/*flags*/0, /*lockfunc*/NULL,
|
|
/*lockarg*/NULL, &sc->parent_dmat) != 0) {
|
|
device_printf(dev, "unable to create dma tag\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
|
|
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
|
/*highaddr*/BUS_SPACE_MAXADDR,
|
|
/*filter*/NULL, /*filterarg*/NULL,
|
|
/*maxsize*/sc->dma_segs * ATI_IXP_NCHANS *
|
|
sizeof(struct atiixp_dma_op),
|
|
/*nsegments*/1, /*maxsegz*/0x3ffff,
|
|
/*flags*/0, /*lockfunc*/NULL,
|
|
/*lockarg*/NULL, &sc->sgd_dmat) != 0) {
|
|
device_printf(dev, "unable to create dma tag\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (bus_dmamem_alloc(sc->sgd_dmat, (void **)&sc->sgd_table,
|
|
BUS_DMA_NOWAIT, &sc->sgd_dmamap) == -1)
|
|
goto bad;
|
|
|
|
if (bus_dmamap_load(sc->sgd_dmat, sc->sgd_dmamap, sc->sgd_table,
|
|
sc->dma_segs * ATI_IXP_NCHANS *
|
|
sizeof(struct atiixp_dma_op),
|
|
atiixp_dma_cb, sc, 0))
|
|
goto bad;
|
|
|
|
|
|
atiixp_chip_pre_init(sc);
|
|
|
|
sc->delayed_attach.ich_func = atiixp_chip_post_init;
|
|
sc->delayed_attach.ich_arg = sc;
|
|
if (cold == 0 ||
|
|
config_intrhook_establish(&sc->delayed_attach) != 0) {
|
|
sc->delayed_attach.ich_func = NULL;
|
|
atiixp_chip_post_init(sc);
|
|
}
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
if (sc->codec)
|
|
ac97_destroy(sc->codec);
|
|
if (sc->ih)
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
if (sc->reg)
|
|
bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
|
|
if (sc->irq)
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
if (sc->parent_dmat)
|
|
bus_dma_tag_destroy(sc->parent_dmat);
|
|
if (sc->sgd_dmamap)
|
|
bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap);
|
|
if (sc->sgd_dmat)
|
|
bus_dma_tag_destroy(sc->sgd_dmat);
|
|
if (sc->lock)
|
|
snd_mtxfree(sc->lock);
|
|
free(sc, M_DEVBUF);
|
|
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
atiixp_pci_detach(device_t dev)
|
|
{
|
|
int r;
|
|
struct atiixp_info *sc;
|
|
|
|
r = pcm_unregister(dev);
|
|
if (r)
|
|
return r;
|
|
|
|
sc = pcm_getdevinfo(dev);
|
|
|
|
atiixp_disable_interrupts(sc);
|
|
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
bus_dma_tag_destroy(sc->parent_dmat);
|
|
bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap);
|
|
bus_dma_tag_destroy(sc->sgd_dmat);
|
|
snd_mtxfree(sc->lock);
|
|
free(sc, M_DEVBUF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
atiixp_pci_suspend(device_t dev)
|
|
{
|
|
struct atiixp_info *sc = pcm_getdevinfo(dev);
|
|
uint32_t value;
|
|
|
|
/* quickly disable interrupts and save channels active state */
|
|
atiixp_lock(sc);
|
|
atiixp_disable_interrupts(sc);
|
|
value = atiixp_rd(sc, ATI_REG_CMD);
|
|
sc->pch.active = (value & ATI_REG_CMD_SEND_EN) ? 1 : 0;
|
|
sc->rch.active = (value & ATI_REG_CMD_RECEIVE_EN) ? 1 : 0;
|
|
atiixp_unlock(sc);
|
|
|
|
/* stop everything */
|
|
if (sc->pch.channel && sc->pch.active)
|
|
atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_STOP);
|
|
if (sc->rch.channel && sc->rch.active)
|
|
atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_STOP);
|
|
|
|
/* power down aclink and pci bus */
|
|
atiixp_lock(sc);
|
|
value = atiixp_rd(sc, ATI_REG_CMD);
|
|
value |= ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET;
|
|
atiixp_wr(sc, ATI_REG_CMD, ATI_REG_CMD_POWERDOWN);
|
|
pci_set_powerstate(dev, PCI_POWERSTATE_D3);
|
|
atiixp_unlock(sc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
atiixp_pci_resume(device_t dev)
|
|
{
|
|
struct atiixp_info *sc = pcm_getdevinfo(dev);
|
|
|
|
atiixp_lock(sc);
|
|
/* power up pci bus */
|
|
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
|
pci_enable_io(dev, SYS_RES_MEMORY);
|
|
pci_enable_busmaster(dev);
|
|
/* reset / power up aclink */
|
|
atiixp_reset_aclink(sc);
|
|
atiixp_unlock(sc);
|
|
|
|
if (mixer_reinit(dev) == -1) {
|
|
device_printf(dev, "unable to reinitialize the mixer\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
/*
|
|
* Resume channel activities. Reset channel format regardless
|
|
* of its previous state.
|
|
*/
|
|
if (sc->pch.channel) {
|
|
if (sc->pch.fmt)
|
|
atiixp_chan_setformat(NULL, &sc->pch, sc->pch.fmt);
|
|
if (sc->pch.active)
|
|
atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_START);
|
|
}
|
|
if (sc->rch.channel) {
|
|
if (sc->rch.fmt)
|
|
atiixp_chan_setformat(NULL, &sc->rch, sc->rch.fmt);
|
|
if (sc->rch.active)
|
|
atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_START);
|
|
}
|
|
|
|
/* enable interrupts */
|
|
atiixp_lock(sc);
|
|
atiixp_enable_interrupts(sc);
|
|
atiixp_unlock(sc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static device_method_t atiixp_methods[] = {
|
|
DEVMETHOD(device_probe, atiixp_pci_probe),
|
|
DEVMETHOD(device_attach, atiixp_pci_attach),
|
|
DEVMETHOD(device_detach, atiixp_pci_detach),
|
|
DEVMETHOD(device_suspend, atiixp_pci_suspend),
|
|
DEVMETHOD(device_resume, atiixp_pci_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t atiixp_driver = {
|
|
"pcm",
|
|
atiixp_methods,
|
|
PCM_SOFTC_SIZE,
|
|
};
|
|
|
|
DRIVER_MODULE(snd_atiixp, pci, atiixp_driver, pcm_devclass, 0, 0);
|
|
MODULE_DEPEND(snd_atiixp, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
|
MODULE_VERSION(snd_atiixp, 1);
|