2914706ab0
Summary: Powerpc64 has support for a register called Data Stream Control Register (DSCR), which basically controls how the hardware controls the caching and prefetch for stream operations. Since mfdscr and mtdscr are privileged instructions, we need to emulate them, and keep the custom DSCR configuration per thread. The purpose of this feature is to change DSCR depending on the operation, set to DSCR Default Prefetch Depth to deepest on string operations, as memcpy. Submitted by: Breno Leitao Differential Revision: https://reviews.freebsd.org/D15081
105 lines
3.5 KiB
C
105 lines
3.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: pcb.h,v 1.4 2000/06/04 11:57:17 tsubai Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PCB_H_
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#define _MACHINE_PCB_H_
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#include <machine/setjmp.h>
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#ifndef _STANDALONE
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struct pcb {
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register_t pcb_context[20]; /* non-volatile r14-r31 */
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register_t pcb_cr; /* Condition register */
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register_t pcb_sp; /* stack pointer */
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register_t pcb_toc; /* toc pointer */
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register_t pcb_lr; /* link register */
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register_t pcb_dscr; /* dscr value */
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struct pmap *pcb_pm; /* pmap of our vmspace */
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jmp_buf *pcb_onfault; /* For use during
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copyin/copyout */
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int pcb_flags;
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#define PCB_FPU 0x1 /* Process uses FPU */
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#define PCB_FPREGS 0x2 /* Process had FPU registers initialized */
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#define PCB_VEC 0x4 /* Process had Altivec initialized */
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#define PCB_VSX 0x8 /* Process had VSX initialized */
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#define PCB_CDSCR 0x10 /* Process had Custom DSCR initialized */
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struct fpu {
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union {
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double fpr;
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uint32_t vsr[4];
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} fpr[32];
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double fpscr; /* FPSCR stored as double for easier access */
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} pcb_fpu; /* Floating point processor */
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unsigned int pcb_fpcpu; /* which CPU had our FPU
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stuff. */
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struct vec {
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uint32_t vr[32][4];
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uint32_t spare[2];
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uint32_t vrsave;
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uint32_t vscr; /* aligned at vector element 3 */
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} pcb_vec __aligned(16); /* Vector processor */
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unsigned int pcb_veccpu; /* which CPU had our vector
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stuff. */
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union {
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struct {
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vm_offset_t usr_segm; /* Base address */
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register_t usr_vsid; /* USER_SR segment */
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} aim;
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struct {
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register_t dbcr0;
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} booke;
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} pcb_cpu;
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};
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#endif
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#ifdef _KERNEL
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struct trapframe;
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#ifndef curpcb
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extern struct pcb *curpcb;
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#endif
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extern struct pmap *curpm;
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extern struct proc *fpuproc;
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void makectx(struct trapframe *, struct pcb *);
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void savectx(struct pcb *) __returns_twice;
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#endif
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#endif /* _MACHINE_PCB_H_ */
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