Landon J. Fuller 824b48eff3 bhnd(4): Implement backplane interrupt handling. ... This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit)		2016-09-05 22:11:46 +00:00
..
bwn_mac.c	bhnd(4): Implement backplane interrupt handling.	2016-09-05 22:11:46 +00:00
if_bwn_chipid.h
if_bwn_cordic.h
if_bwn_debug.h
if_bwn_misc.h
if_bwn_pci.c	bwn(4): ignore BCM4321's unpopulated USB11 host controller core.	2016-09-05 21:55:27 +00:00
if_bwn_pcivar.h	bwn(4): ignore BCM4321's unpopulated USB11 host controller core.	2016-09-05 21:55:27 +00:00
if_bwn_phy_common.c
if_bwn_phy_common.h
if_bwn_phy_g.c
if_bwn_phy_g.h
if_bwn_phy_lp.c
if_bwn_phy_lp.h
if_bwn_phy_n.c
if_bwn_phy_n.h
if_bwn_util.c
if_bwn_util.h
if_bwn.c	[bwn] don't use a 1MB CCK RTS frame for 11a OFDM transmissions.	2016-06-06 07:09:02 +00:00
if_bwnreg.h
if_bwnvar.h