7282444b10
Mainly focus on files that use BSD 3-Clause license. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Special thanks to Wind River for providing access to "The Duke of Highlander" tool: an older (2014) run over FreeBSD tree was useful as a starting point.
500 lines
16 KiB
C
500 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2007 The DragonFly Project. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Sepherosa Ziehau <sepherosa@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.4 2007/10/19 14:27:04 sephe Exp $
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* $FreeBSD$
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*/
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#ifndef _IF_BWIREG_H
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#define _IF_BWIREG_H
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/*
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* Registers for all of the register windows
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*/
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#define BWI_FLAGS 0xf18
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#define BWI_FLAGS_INTR_MASK __BITS(5, 0)
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#define BWI_IMSTATE 0xf90
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#define BWI_IMSTATE_INBAND_ERR __BIT(17)
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#define BWI_IMSTATE_TIMEOUT __BIT(18)
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#define BWI_INTRVEC 0xf94
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#define BWI_STATE_LO 0xf98
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#define BWI_STATE_LO_RESET __BIT(0)
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#define BWI_STATE_LO_DISABLE1 __BIT(1)
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#define BWI_STATE_LO_DISABLE2 __BIT(2)
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#define BWI_STATE_LO_CLOCK __BIT(16)
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#define BWI_STATE_LO_GATED_CLOCK __BIT(17)
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#define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0)
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#define BWI_STATE_LO_FLAG_PHYRST __BIT(1)
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#define BWI_STATE_LO_FLAG_PHYLNK __BIT(11)
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#define BWI_STATE_LO_FLAGS_MASK __BITS(29, 18)
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#define BWI_STATE_HI 0xf9c
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#define BWI_STATE_HI_SERROR __BIT(0)
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#define BWI_STATE_HI_BUSY __BIT(2)
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#define BWI_STATE_HI_FLAG_MAGIC1 0x1
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#define BWI_STATE_HI_FLAG_MAGIC2 0x2
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#define BWI_STATE_HI_FLAG_64BIT 0x1000
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#define BWI_STATE_HI_FLAGS_MASK __BITS(28, 16)
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#define BWI_CONF_LO 0xfa8
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#define BWI_CONF_LO_SERVTO_MASK __BITS(2, 0) /* service timeout */
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#define BWI_CONF_LO_SERVTO 2
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#define BWI_CONF_LO_REQTO_MASK __BITS(6, 4) /* request timeout */
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#define BWI_CONF_LO_REQTO 3
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#define BWI_ID_LO 0xff8
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#define BWI_ID_LO_BUSREV_MASK __BITS(31, 28)
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/* Bus revision */
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#define BWI_BUSREV_0 0
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#define BWI_BUSREV_1 1
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#define BWI_ID_HI 0xffc
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#define BWI_ID_HI_REGWIN_REV(v) (((v) & 0xf) | (((v) & 0x7000) >> 8))
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#define BWI_ID_HI_REGWIN_TYPE(v) (((v) & 0x8ff0) >> 4)
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#define BWI_ID_HI_REGWIN_VENDOR_MASK __BITS(31, 16)
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/*
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* Registers for common register window
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*/
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#define BWI_INFO 0x0
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#define BWI_INFO_BBPID_MASK __BITS(15, 0)
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#define BWI_INFO_BBPREV_MASK __BITS(19, 16)
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#define BWI_INFO_BBPPKG_MASK __BITS(23, 20)
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#define BWI_INFO_NREGWIN_MASK __BITS(27, 24)
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#define BWI_CAPABILITY 0x4
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#define BWI_CAP_CLKMODE __BIT(18)
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#define BWI_CONTROL 0x28
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#define BWI_CONTROL_MAGIC0 0x3a4
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#define BWI_CONTROL_MAGIC1 0xa4
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#define BWI_PLL_ON_DELAY 0xb0
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#define BWI_FREQ_SEL_DELAY 0xb4
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#define BWI_CLOCK_CTRL 0xb8
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#define BWI_CLOCK_CTRL_CLKSRC __BITS(2, 0)
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#define BWI_CLOCK_CTRL_SLOW __BIT(11)
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#define BWI_CLOCK_CTRL_IGNPLL __BIT(12)
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#define BWI_CLOCK_CTRL_NODYN __BIT(13)
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#define BWI_CLOCK_CTRL_FDIV __BITS(31, 16) /* freq divisor */
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/* Possible values for BWI_CLOCK_CTRL_CLKSRC */
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#define BWI_CLKSRC_LP_OSC 0 /* Low power oscillator */
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#define BWI_CLKSRC_CS_OSC 1 /* Crystal oscillator */
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#define BWI_CLKSRC_PCI 2
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#define BWI_CLKSRC_MAX 3 /* Maximum of clock source */
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/* Min/Max frequency for given clock source */
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#define BWI_CLKSRC_LP_OSC_FMIN 25000
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#define BWI_CLKSRC_LP_OSC_FMAX 43000
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#define BWI_CLKSRC_CS_OSC_FMIN 19800000
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#define BWI_CLKSRC_CS_OSC_FMAX 20200000
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#define BWI_CLKSRC_PCI_FMIN 25000000
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#define BWI_CLKSRC_PCI_FMAX 34000000
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#define BWI_CLOCK_INFO 0xc0
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#define BWI_CLOCK_INFO_FDIV __BITS(31, 16) /* freq divisor */
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/*
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* Registers for bus register window
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*/
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#define BWI_BUS_ADDR 0x50
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#define BWI_BUS_ADDR_MAGIC 0xfd8
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#define BWI_BUS_DATA 0x54
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#define BWI_BUS_CONFIG 0x108
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#define BWI_BUS_CONFIG_PREFETCH __BIT(2)
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#define BWI_BUS_CONFIG_BURST __BIT(3)
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#define BWI_BUS_CONFIG_MRM __BIT(5)
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/*
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* Register for MAC
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*/
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#define BWI_TXRX_INTR_STATUS_BASE 0x20
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#define BWI_TXRX_INTR_MASK_BASE 0x24
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#define BWI_TXRX_INTR_STATUS(i) (BWI_TXRX_INTR_STATUS_BASE + ((i) * 8))
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#define BWI_TXRX_INTR_MASK(i) (BWI_TXRX_INTR_MASK_BASE + ((i) * 8))
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#define BWI_MAC_STATUS 0x120
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#define BWI_MAC_STATUS_ENABLE __BIT(0)
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#define BWI_MAC_STATUS_UCODE_START __BIT(1)
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#define BWI_MAC_STATUS_UCODE_JUMP0 __BIT(2)
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#define BWI_MAC_STATUS_IHREN __BIT(10)
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#define BWI_MAC_STATUS_GPOSEL_MASK __BITS(15, 14)
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#define BWI_MAC_STATUS_BSWAP __BIT(16)
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#define BWI_MAC_STATUS_INFRA __BIT(17)
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#define BWI_MAC_STATUS_OPMODE_HOSTAP __BIT(18)
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#define BWI_MAC_STATUS_RFLOCK __BIT(19)
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#define BWI_MAC_STATUS_PASS_BCN __BIT(20)
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#define BWI_MAC_STATUS_PASS_BADPLCP __BIT(21)
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#define BWI_MAC_STATUS_PASS_CTL __BIT(22)
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#define BWI_MAC_STATUS_PASS_BADFCS __BIT(23)
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#define BWI_MAC_STATUS_PROMISC __BIT(24)
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#define BWI_MAC_STATUS_HW_PS __BIT(25)
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#define BWI_MAC_STATUS_WAKEUP __BIT(26)
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#define BWI_MAC_STATUS_PHYLNK __BIT(31)
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#define BWI_MAC_INTR_STATUS 0x128
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#define BWI_MAC_INTR_MASK 0x12c
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#define BWI_MAC_TMPLT_CTRL 0x130
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#define BWI_MAC_TMPLT_DATA 0x134
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#define BWI_MAC_PS_STATUS 0x140
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#define BWI_MOBJ_CTRL 0x160
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#define BWI_MOBJ_CTRL_VAL(objid, ofs) ((objid) << 16 | (ofs))
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#define BWI_MOBJ_DATA 0x164
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#define BWI_MOBJ_DATA_UNALIGN 0x166
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/*
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* Memory object IDs
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*/
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#define BWI_WR_MOBJ_AUTOINC 0x100 /* Auto-increment wr */
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#define BWI_RD_MOBJ_AUTOINC 0x200 /* Auto-increment rd */
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/* Firmware ucode object */
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#define BWI_FW_UCODE_MOBJ 0x0
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/* Common object */
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#define BWI_COMM_MOBJ 0x1
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#define BWI_COMM_MOBJ_FWREV 0x0
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#define BWI_COMM_MOBJ_FWPATCHLV 0x2
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#define BWI_COMM_MOBJ_SLOTTIME 0x10
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#define BWI_COMM_MOBJ_MACREV 0x16
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#define BWI_COMM_MOBJ_TX_ACK 0x22
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#define BWI_COMM_MOBJ_UCODE_STATE 0x40
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#define BWI_COMM_MOBJ_SHRETRY_FB 0x44
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#define BWI_COMM_MOBJ_LGRETEY_FB 0x46
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#define BWI_COMM_MOBJ_TX_BEACON 0x54
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#define BWI_COMM_MOBJ_KEYTABLE_OFS 0x56
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#define BWI_COMM_MOBJ_TSSI_DS 0x58
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#define BWI_COMM_MOBJ_HFLAGS_LO 0x5e
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#define BWI_COMM_MOBJ_HFLAGS_MI 0x60
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#define BWI_COMM_MOBJ_HFLAGS_HI 0x62
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#define BWI_COMM_MOBJ_RF_ATTEN 0x64
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#define BWI_COMM_MOBJ_RF_NOISE 0x6e
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#define BWI_COMM_MOBJ_TSSI_OFDM 0x70
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#define BWI_COMM_MOBJ_PROBE_RESP_TO 0x74
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#define BWI_COMM_MOBJ_CHAN 0xa0
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#define BWI_COMM_MOBJ_KEY_ALGO 0x100
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#define BWI_COMM_MOBJ_TX_PROBE_RESP 0x188
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#define BWI_HFLAG_AUTO_ANTDIV 0x1ULL
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#define BWI_HFLAG_SYM_WA 0x2ULL /* ??? SYM work around */
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#define BWI_HFLAG_PWR_BOOST_DS 0x8ULL
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#define BWI_HFLAG_GDC_WA 0x20ULL /* ??? GDC work around */
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#define BWI_HFLAG_OFDM_PA 0x40ULL
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#define BWI_HFLAG_NOT_JAPAN 0x80ULL
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#define BWI_HFLAG_MAGIC1 0x200ULL
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#define BWI_UCODE_STATE_PS 4
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#define BWI_LO_TSSI_MASK __BITS(7, 0)
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#define BWI_HI_TSSI_MASK __BITS(15, 8)
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#define BWI_INVALID_TSSI 0x7f
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/* 802.11 object */
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#define BWI_80211_MOBJ 0x2
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#define BWI_80211_MOBJ_CWMIN 0xc
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#define BWI_80211_MOBJ_CWMAX 0x10
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#define BWI_80211_MOBJ_SHRETRY 0x18
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#define BWI_80211_MOBJ_LGRETRY 0x1c
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/* Firmware PCM object */
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#define BWI_FW_PCM_MOBJ 0x3
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/* MAC address of pairwise keys */
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#define BWI_PKEY_ADDR_MOBJ 0x4
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#define BWI_TXSTATUS0 0x170
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#define BWI_TXSTATUS0_VALID __BIT(0)
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#define BWI_TXSTATUS0_ACKED __BIT(1)
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#define BWI_TXSTATUS0_FREASON_MASK __BITS(4, 2) /* Failure reason */
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#define BWI_TXSTATUS0_AMPDU __BIT(5)
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#define BWI_TXSTATUS0_PENDING __BIT(6)
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#define BWI_TXSTATUS0_PM __BIT(7)
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#define BWI_TXSTATUS0_RTS_TXCNT_MASK __BITS(11, 8)
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#define BWI_TXSTATUS0_DATA_TXCNT_MASK __BITS(15, 12)
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#define BWI_TXSTATUS0_TXID_MASK __BITS(31, 16)
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#define BWI_TXSTATUS1 0x174
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#define BWI_TXRX_CTRL_BASE 0x200
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#define BWI_TX32_CTRL 0x0
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#define BWI_TX32_RINGINFO 0x4
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#define BWI_TX32_INDEX 0x8
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#define BWI_TX32_STATUS 0xc
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#define BWI_TX32_STATUS_STATE_MASK __BITS(15, 12)
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#define BWI_TX32_STATUS_STATE_DISABLED 0
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#define BWI_TX32_STATUS_STATE_IDLE 2
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#define BWI_TX32_STATUS_STATE_STOPPED 3
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#define BWI_RX32_CTRL 0x10
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#define BWI_RX32_CTRL_HDRSZ_MASK __BITS(7, 1)
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#define BWI_RX32_RINGINFO 0x14
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#define BWI_RX32_INDEX 0x18
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#define BWI_RX32_STATUS 0x1c
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#define BWI_RX32_STATUS_INDEX_MASK __BITS(11, 0)
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#define BWI_RX32_STATUS_STATE_MASK __BITS(15, 12)
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#define BWI_RX32_STATUS_STATE_DISABLED 0
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/* Shared by 32bit TX/RX CTRL */
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#define BWI_TXRX32_CTRL_ENABLE __BIT(0)
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#define BWI_TXRX32_CTRL_ADDRHI_MASK __BITS(17, 16)
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/* Shared by 32bit TX/RX RINGINFO */
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#define BWI_TXRX32_RINGINFO_FUNC_TXRX 0x1
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#define BWI_TXRX32_RINGINFO_FUNC_MASK __BITS(31, 30)
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#define BWI_TXRX32_RINGINFO_ADDR_MASK __BITS(29, 0)
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#define BWI_PHYINFO 0x3e0
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#define BWI_PHYINFO_REV_MASK __BITS(3, 0)
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#define BWI_PHYINFO_TYPE_MASK __BITS(11, 8)
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#define BWI_PHYINFO_TYPE_11A 0
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#define BWI_PHYINFO_TYPE_11B 1
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#define BWI_PHYINFO_TYPE_11G 2
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#define BWI_PHYINFO_TYPE_11N 4
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#define BWI_PHYINFO_TYPE_11LP 5
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#define BWI_PHYINFO_VER_MASK __BITS(15, 12)
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#define BWI_RF_ANTDIV 0x3e2 /* Antenna Diversity?? */
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#define BWI_PHY_MAGIC_REG1 0x3e4
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#define BWI_PHY_MAGIC_REG1_VAL1 0x3000
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#define BWI_PHY_MAGIC_REG1_VAL2 0x9
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#define BWI_BBP_ATTEN 0x3e6
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#define BWI_BBP_ATTEN_MAGIC 0xf4
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#define BWI_BBP_ATTEN_MAGIC2 0x8140
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#define BWI_BPHY_CTRL 0x3ec
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#define BWI_BPHY_CTRL_INIT 0x3f22
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#define BWI_RF_CHAN 0x3f0
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#define BWI_RF_CHAN_EX 0x3f4
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#define BWI_RF_CTRL 0x3f6
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/* Register values for BWI_RF_CTRL */
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#define BWI_RF_CTRL_RFINFO 0x1
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/* XXX extra bits for reading from radio */
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#define BWI_RF_CTRL_RD_11A 0x40
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#define BWI_RF_CTRL_RD_11BG 0x80
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#define BWI_RF_DATA_HI 0x3f8
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#define BWI_RF_DATA_LO 0x3fa
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/* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */
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#define BWI_RFINFO_MANUFACT_MASK __BITS(11, 0)
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#define BWI_RF_MANUFACT_BCM 0x17f /* XXX */
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#define BWI_RFINFO_TYPE_MASK __BITS(27, 12)
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#define BWI_RF_T_BCM2050 0x2050
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#define BWI_RF_T_BCM2053 0x2053
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#define BWI_RF_T_BCM2060 0x2060
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#define BWI_RFINFO_REV_MASK __BITS(31, 28)
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#define BWI_PHY_CTRL 0x3fc
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#define BWI_PHY_DATA 0x3fe
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#define BWI_ADDR_FILTER_CTRL 0x420
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#define BWI_ADDR_FILTER_CTRL_SET 0x20
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#define BWI_ADDR_FILTER_MYADDR 0
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#define BWI_ADDR_FILTER_BSSID 3
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#define BWI_ADDR_FILTER_DATA 0x422
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#define BWI_MAC_GPIO_CTRL 0x49c
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#define BWI_MAC_GPIO_MASK 0x49e
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#define BWI_MAC_PRE_TBTT 0x612
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#define BWI_MAC_SLOTTIME 0x684
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#define BWI_MAC_SLOTTIME_ADJUST 510
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#define BWI_MAC_POWERUP_DELAY 0x6a8
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/*
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* Special registers
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*/
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/*
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* GPIO control
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* If common regwin exists, then it is within common regwin,
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* else it is in bus regwin.
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*/
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#define BWI_GPIO_CTRL 0x6c
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#define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */
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#define PCI_PRODUCT_BROADCOM_BCM4309 0x4324
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/*
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* Extended PCI registers
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*/
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#define BWI_PCIR_BAR PCIR_BAR(0)
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#define BWI_PCIR_SEL_REGWIN 0x80
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/* Register value for BWI_PCIR_SEL_REGWIN */
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#define BWI_PCIM_REGWIN(id) (((id) * 0x1000) + 0x18000000)
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#define BWI_PCIR_GPIO_IN 0xb0
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#define BWI_PCIR_GPIO_OUT 0xb4
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#define BWI_PCIM_GPIO_OUT_CLKSRC __BIT(4)
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#define BWI_PCIR_GPIO_ENABLE 0xb8
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/* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */
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#define BWI_PCIM_GPIO_PWR_ON __BIT(6)
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#define BWI_PCIM_GPIO_PLL_PWR_OFF __BIT(7)
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#define BWI_PCIR_INTCTL 0x94
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/*
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* PCI subdevice IDs
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*/
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#define BWI_PCI_SUBDEVICE_BU4306 0x416
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#define BWI_PCI_SUBDEVICE_BCM4309G 0x421
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#define BWI_IS_BRCM_BU4306(sc) \
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((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \
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(sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306)
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#define BWI_IS_BRCM_BCM4309G(sc) \
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((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \
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(sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G)
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/*
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* EEPROM start address
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*/
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#define BWI_SPROM_START 0x1000
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#define BWI_SPROM_11BG_EADDR 0x48
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#define BWI_SPROM_11A_EADDR 0x54
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#define BWI_SPROM_CARD_INFO 0x5c
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#define BWI_SPROM_CARD_INFO_LOCALE __BITS(11, 8)
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#define BWI_SPROM_LOCALE_JAPAN 5
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#define BWI_SPROM_PA_PARAM_11BG 0x5e
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#define BWI_SPROM_GPIO01 0x64
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#define BWI_SPROM_GPIO_0 __BITS(7, 0)
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#define BWI_SPROM_GPIO_1 __BITS(15, 8)
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#define BWI_SPROM_GPIO23 0x66
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#define BWI_SPROM_GPIO_2 __BITS(7, 0)
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#define BWI_SPROM_GPIO_3 __BITS(15, 8)
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#define BWI_SPROM_MAX_TXPWR 0x68
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#define BWI_SPROM_MAX_TXPWR_MASK_11BG __BITS(7, 0) /* XXX */
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#define BWI_SPROM_MAX_TXPWR_MASK_11A __BITS(15, 8) /* XXX */
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#define BWI_SPROM_PA_PARAM_11A 0x6a
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#define BWI_SPROM_IDLE_TSSI 0x70
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#define BWI_SPROM_IDLE_TSSI_MASK_11BG __BITS(7, 0) /* XXX */
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#define BWI_SPROM_IDLE_TSSI_MASK_11A __BITS(15, 8) /* XXX */
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#define BWI_SPROM_CARD_FLAGS 0x72
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#define BWI_SPROM_ANT_GAIN 0x74
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#define BWI_SPROM_ANT_GAIN_MASK_11A __BITS(7, 0)
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#define BWI_SPROM_ANT_GAIN_MASK_11BG __BITS(15, 8)
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/*
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* SPROM card flags
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*/
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#define BWI_CARD_F_BT_COEXIST __BIT(0) /* Bluetooth coexist */
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#define BWI_CARD_F_PA_GPIO9 __BIT(1) /* GPIO 9 controls PA */
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#define BWI_CARD_F_SW_NRSSI __BIT(3)
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#define BWI_CARD_F_NO_SLOWCLK __BIT(5) /* no slow clock */
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#define BWI_CARD_F_EXT_LNA __BIT(12) /* external LNA */
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#define BWI_CARD_F_ALT_IQ __BIT(15) /* alternate I/Q */
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/*
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* SPROM GPIO
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*/
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#define BWI_LED_ACT_LOW __BIT(7)
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#define BWI_LED_ACT_MASK __BITS(6, 0)
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#define BWI_LED_ACT_OFF 0
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#define BWI_LED_ACT_ON 1
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#define BWI_LED_ACT_BLINK 2
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#define BWI_LED_ACT_RF_ENABLED 3
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#define BWI_LED_ACT_5GHZ 4
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#define BWI_LED_ACT_2GHZ 5
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#define BWI_LED_ACT_11G 6
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#define BWI_LED_ACT_BLINK_SLOW 7
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#define BWI_LED_ACT_BLINK_POLL 8
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#define BWI_LED_ACT_UNKN 9
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#define BWI_LED_ACT_ASSOC 10
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#define BWI_LED_ACT_NULL 11
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#define BWI_VENDOR_LED_ACT_COMPAQ \
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BWI_LED_ACT_RF_ENABLED, \
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BWI_LED_ACT_2GHZ, \
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BWI_LED_ACT_5GHZ, \
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BWI_LED_ACT_OFF
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#define BWI_VENDOR_LED_ACT_LINKSYS \
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BWI_LED_ACT_ASSOC, \
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BWI_LED_ACT_2GHZ, \
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BWI_LED_ACT_5GHZ, \
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BWI_LED_ACT_OFF
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#define BWI_VENDOR_LED_ACT_DEFAULT \
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BWI_LED_ACT_BLINK, \
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BWI_LED_ACT_2GHZ, \
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BWI_LED_ACT_5GHZ, \
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BWI_LED_ACT_OFF
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/*
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* BBP IDs
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*/
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#define BWI_BBPID_BCM4301 0x4301
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#define BWI_BBPID_BCM4306 0x4306
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#define BWI_BBPID_BCM4317 0x4317
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#define BWI_BBPID_BCM4320 0x4320
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#define BWI_BBPID_BCM4321 0x4321
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/*
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* Register window types
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*/
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#define BWI_REGWIN_T_COM 0x800
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#define BWI_REGWIN_T_BUSPCI 0x804
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#define BWI_REGWIN_T_MAC 0x812
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#define BWI_REGWIN_T_BUSPCIE 0x820
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/*
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* MAC interrupts
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*/
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#define BWI_INTR_READY __BIT(0)
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#define BWI_INTR_BEACON __BIT(1)
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#define BWI_INTR_TBTT __BIT(2)
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#define BWI_INTR_EO_ATIM __BIT(5) /* End of ATIM */
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#define BWI_INTR_PMQ __BIT(6) /* XXX?? */
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#define BWI_INTR_MAC_TXERR __BIT(9)
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#define BWI_INTR_PHY_TXERR __BIT(11)
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#define BWI_INTR_TIMER1 __BIT(14)
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#define BWI_INTR_RX_DONE __BIT(15)
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#define BWI_INTR_TX_FIFO __BIT(16) /* XXX?? */
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#define BWI_INTR_NOISE __BIT(18)
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#define BWI_INTR_RF_DISABLED __BIT(28)
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#define BWI_INTR_TX_DONE __BIT(29)
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#define BWI_INIT_INTRS \
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(BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \
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BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \
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BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \
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BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE)
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#define BWI_ALL_INTRS 0xffffffff
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/*
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* TX/RX interrupts
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*/
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#define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10))
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#define BWI_TXRX_INTR_RX __BIT(16)
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#define BWI_TXRX_TX_INTRS BWI_TXRX_INTR_ERROR
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#define BWI_TXRX_RX_INTRS (BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX)
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#define BWI_TXRX_IS_RX(i) ((i) % 3 == 0)
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#endif /* !_IF_BWIREG_H */
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