f785676f2a
all of the features in the current working draft of the upcoming C++ standard, provisionally named C++1y. The code generator's performance is greatly increased, and the loop auto-vectorizer is now enabled at -Os and -O2 in addition to -O3. The PowerPC backend has made several major improvements to code generation quality and compile time, and the X86, SPARC, ARM32, Aarch64 and SystemZ backends have all seen major feature work. Release notes for llvm and clang can be found here: <http://llvm.org/releases/3.4/docs/ReleaseNotes.html> <http://llvm.org/releases/3.4/tools/clang/docs/ReleaseNotes.html> MFC after: 1 month
351 lines
7.9 KiB
Groff
351 lines
7.9 KiB
Groff
.\" $FreeBSD$
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.\" Man page generated from reStructuredText.
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.TH "LLI" "1" "2014-01-01" "3.4" "LLVM"
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.SH NAME
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lli \- directly execute programs from LLVM bitcode
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.SH SYNOPSIS
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.sp
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\fBlli\fP [\fIoptions\fP] [\fIfilename\fP] [\fIprogram args\fP]
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.SH DESCRIPTION
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.sp
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\fBlli\fP directly executes programs in LLVM bitcode format. It takes a program
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in LLVM bitcode format and executes it using a just\-in\-time compiler, if one is
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available for the current architecture, or an interpreter. \fBlli\fP takes all of
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the same code generator options as llc|llc, but they are only effective when
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\fBlli\fP is using the just\-in\-time compiler.
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.sp
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If \fIfilename\fP is not specified, then \fBlli\fP reads the LLVM bitcode for the
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program from standard input.
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.sp
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The optional \fIargs\fP specified on the command line are passed to the program as
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arguments.
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.SH GENERAL OPTIONS
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.sp
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\fB\-fake\-argv0\fP=\fIexecutable\fP
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.INDENT 0.0
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.INDENT 3.5
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Override the \fBargv[0]\fP value passed into the executing program.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-force\-interpreter\fP=\fI{false,true}\fP
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.INDENT 0.0
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.INDENT 3.5
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If set to true, use the interpreter even if a just\-in\-time compiler is available
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for this architecture. Defaults to false.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-help\fP
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.INDENT 0.0
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.INDENT 3.5
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Print a summary of command line options.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-load\fP=\fIpluginfilename\fP
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.INDENT 0.0
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.INDENT 3.5
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Causes \fBlli\fP to load the plugin (shared object) named \fIpluginfilename\fP and use
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it for optimization.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-stats\fP
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.INDENT 0.0
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.INDENT 3.5
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Print statistics from the code\-generation passes. This is only meaningful for
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the just\-in\-time compiler, at present.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-time\-passes\fP
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.INDENT 0.0
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.INDENT 3.5
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Record the amount of time needed for each code\-generation pass and print it to
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standard error.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-version\fP
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.INDENT 0.0
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.INDENT 3.5
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Print out the version of \fBlli\fP and exit without doing anything else.
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.UNINDENT
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.UNINDENT
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.SH TARGET OPTIONS
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.sp
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\fB\-mtriple\fP=\fItarget triple\fP
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.INDENT 0.0
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.INDENT 3.5
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Override the target triple specified in the input bitcode file with the
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specified string. This may result in a crash if you pick an
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architecture which is not compatible with the current system.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-march\fP=\fIarch\fP
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.INDENT 0.0
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.INDENT 3.5
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Specify the architecture for which to generate assembly, overriding the target
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encoded in the bitcode file. See the output of \fBllc \-help\fP for a list of
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valid architectures. By default this is inferred from the target triple or
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autodetected to the current architecture.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-mcpu\fP=\fIcpuname\fP
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.INDENT 0.0
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.INDENT 3.5
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Specify a specific chip in the current architecture to generate code for.
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By default this is inferred from the target triple and autodetected to
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the current architecture. For a list of available CPUs, use:
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\fBllvm\-as < /dev/null | llc \-march=xyz \-mcpu=help\fP
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-mattr\fP=\fIa1,+a2,\-a3,...\fP
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.INDENT 0.0
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.INDENT 3.5
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Override or control specific attributes of the target, such as whether SIMD
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operations are enabled or not. The default set of attributes is set by the
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current CPU. For a list of available attributes, use:
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\fBllvm\-as < /dev/null | llc \-march=xyz \-mattr=help\fP
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.UNINDENT
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.UNINDENT
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.SH FLOATING POINT OPTIONS
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.sp
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\fB\-disable\-excess\-fp\-precision\fP
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.INDENT 0.0
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.INDENT 3.5
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Disable optimizations that may increase floating point precision.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-enable\-no\-infs\-fp\-math\fP
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.INDENT 0.0
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.INDENT 3.5
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Enable optimizations that assume no Inf values.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-enable\-no\-nans\-fp\-math\fP
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.INDENT 0.0
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.INDENT 3.5
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Enable optimizations that assume no NAN values.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-enable\-unsafe\-fp\-math\fP
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.INDENT 0.0
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.INDENT 3.5
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Causes \fBlli\fP to enable optimizations that may decrease floating point
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precision.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-soft\-float\fP
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.INDENT 0.0
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.INDENT 3.5
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Causes \fBlli\fP to generate software floating point library calls instead of
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equivalent hardware instructions.
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.UNINDENT
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.UNINDENT
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.SH CODE GENERATION OPTIONS
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.sp
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\fB\-code\-model\fP=\fImodel\fP
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.INDENT 0.0
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.INDENT 3.5
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Choose the code model from:
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.INDENT 0.0
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.INDENT 3.5
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.sp
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.nf
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.ft C
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default: Target default code model
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small: Small code model
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kernel: Kernel code model
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medium: Medium code model
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large: Large code model
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.ft P
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.fi
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-disable\-post\-RA\-scheduler\fP
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.INDENT 0.0
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.INDENT 3.5
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Disable scheduling after register allocation.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-disable\-spill\-fusing\fP
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.INDENT 0.0
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.INDENT 3.5
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Disable fusing of spill code into instructions.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-enable\-correct\-eh\-support\fP
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.INDENT 0.0
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.INDENT 3.5
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Make the \-lowerinvoke pass insert expensive, but correct, EH code.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-jit\-enable\-eh\fP
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.INDENT 0.0
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.INDENT 3.5
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Exception handling should be enabled in the just\-in\-time compiler.
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-join\-liveintervals\fP
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.INDENT 0.0
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.INDENT 3.5
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Coalesce copies (default=true).
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-nozero\-initialized\-in\-bss\fP Don\(aqt place zero\-initialized symbols into the BSS section.
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.sp
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\fB\-pre\-RA\-sched\fP=\fIscheduler\fP
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.INDENT 0.0
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.INDENT 3.5
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Instruction schedulers available (before register allocation):
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.INDENT 0.0
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.INDENT 3.5
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.sp
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.nf
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.ft C
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=default: Best scheduler for the target
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=none: No scheduling: breadth first sequencing
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=simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
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=simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency
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=list\-burr: Bottom\-up register reduction list scheduling
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=list\-tdrr: Top\-down register reduction list scheduling
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=list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code
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.ft P
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.fi
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-regalloc\fP=\fIallocator\fP
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.INDENT 0.0
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.INDENT 3.5
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Register allocator to use (default=linearscan)
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.INDENT 0.0
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.INDENT 3.5
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.sp
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.nf
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.ft C
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=bigblock: Big\-block register allocator
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=linearscan: linear scan register allocator =local \- local register allocator
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=simple: simple register allocator
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.ft P
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.fi
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-relocation\-model\fP=\fImodel\fP
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.INDENT 0.0
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.INDENT 3.5
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Choose relocation model from:
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.INDENT 0.0
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.INDENT 3.5
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.sp
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.nf
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.ft C
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=default: Target default relocation model
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=static: Non\-relocatable code =pic \- Fully relocatable, position independent code
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=dynamic\-no\-pic: Relocatable external references, non\-relocatable code
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.ft P
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.fi
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-spiller\fP
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.INDENT 0.0
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.INDENT 3.5
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Spiller to use (default=local)
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.INDENT 0.0
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.INDENT 3.5
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.sp
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.nf
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.ft C
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=simple: simple spiller
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=local: local spiller
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.ft P
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.fi
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.sp
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\fB\-x86\-asm\-syntax\fP=\fIsyntax\fP
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.INDENT 0.0
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.INDENT 3.5
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Choose style of code to emit from X86 backend:
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.INDENT 0.0
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.INDENT 3.5
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.sp
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.nf
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.ft C
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=att: Emit AT&T\-style assembly
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=intel: Emit Intel\-style assembly
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.ft P
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.fi
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.UNINDENT
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.SH EXIT STATUS
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.sp
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If \fBlli\fP fails to load the program, it will exit with an exit code of 1.
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Otherwise, it will return the exit code of the program it executes.
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.SH SEE ALSO
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.sp
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llc|llc
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.SH AUTHOR
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Maintained by The LLVM Team (http://llvm.org/).
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.SH COPYRIGHT
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2003-2013, LLVM Project
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.\" Generated by docutils manpage writer.
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