ad4c75f74a
Due to hardware limitation AMD I2C controller can't trigger pending interrupt if interrupt status has been changed after clearing interrupt status bits. So, I2C will lose the interrupt and IO will be timed out. Implements a workaround to disable I2C controller interrupt and re-enable I2C interrupt before existing interrupt handler. Submitted by: rajfbsd@gmail.com MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16720
113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/*
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* Copyright (c) 2014 The DragonFly Project. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Matthew Dillon <dillon@backplane.com> and was subsequently ported
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* to FreeBSD by Michael Gmelin <freebsd@grem.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ICHIIC_IG4_VAR_H_
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#define _ICHIIC_IG4_VAR_H_
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#include "bus_if.h"
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#include "device_if.h"
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#include "pci_if.h"
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#include "iicbus_if.h"
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#define IG4_RBUFSIZE 128
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#define IG4_RBUFMASK (IG4_RBUFSIZE - 1)
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enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE };
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enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL };
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struct ig4iic_softc {
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device_t dev;
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struct intr_config_hook enum_hook;
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device_t iicbus;
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struct resource *regs_res;
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int regs_rid;
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struct resource *intr_res;
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int intr_rid;
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void *intr_handle;
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int intr_type;
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enum ig4_vers version;
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enum ig4_op op;
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int cmd;
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int rnext;
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int rpos;
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char rbuf[IG4_RBUFSIZE];
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int error;
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uint8_t last_slave;
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int platform_attached : 1;
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int use_10bit : 1;
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int slave_valid : 1;
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int read_started : 1;
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int write_started : 1;
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int access_intr_mask : 1;
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/*
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* Locking semantics:
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*
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* Functions implementing the icbus interface that interact
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* with the controller acquire an exclusive lock on call_lock
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* to prevent interleaving of calls to the interface and a lock on
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* io_lock right afterwards, to synchronize controller I/O activity.
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*
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* The interrupt handler can only read data while no iicbus call
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* is in progress or while io_lock is dropped during mtx_sleep in
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* wait_status and set_controller. It is safe to drop io_lock in those
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* places, because the interrupt handler only accesses those registers:
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*
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* - IG4_REG_I2C_STA (I2C Status)
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* - IG4_REG_DATA_CMD (Data Buffer and Command)
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* - IG4_REG_CLR_INTR (Clear Interrupt)
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*
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* Locking outside of those places is required to make the content
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* of rpos/rnext predictable (e.g. whenever data_read is called and in
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* ig4iic_transfer).
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*/
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struct sx call_lock;
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struct mtx io_lock;
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};
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typedef struct ig4iic_softc ig4iic_softc_t;
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/* Attach/Detach called from ig4iic_pci_*() */
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int ig4iic_attach(ig4iic_softc_t *sc);
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int ig4iic_detach(ig4iic_softc_t *sc);
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/* iicbus methods */
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extern iicbus_transfer_t ig4iic_transfer;
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extern iicbus_reset_t ig4iic_reset;
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#endif /* _ICHIIC_IG4_VAR_H_ */
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