Zbigniew Bodek 18c72666ce Add domain support to PCI bus allocation ... When the system has more than a single PCI domain, the bus numbers are not unique, thus they cannot be used for "pci" device numbering. Change bus numbers to -1 (i.e. to-be-determined automatically) wherever the code did not care about domains. Reviewed by: jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3406		2015-09-16 23:34:51 +00:00
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apb.c	ACK interrupts on the new SoCs.	2015-01-05 02:00:41 +00:00
apbvar.h	The AR71xx has APB interrupts in the MISC registers from 0-7, later	2014-03-16 08:39:46 +00:00
ar71xx_bus_space_reversed.c
ar71xx_bus_space_reversed.h
ar71xx_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_chip.h
ar71xx_cpudef.h	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_ehci.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_fixup.c
ar71xx_fixup.h
ar71xx_gpio.c	Add GPIO function mux configuration for AR934x SoCs.	2015-03-21 06:08:35 +00:00
ar71xx_gpiovar.h	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
ar71xx_macaddr.c	Begin moving support for board MAC addresses over to being explicitly defined.	2015-03-28 23:40:29 +00:00
ar71xx_macaddr.h	Begin moving support for board MAC addresses over to being explicitly defined.	2015-03-28 23:40:29 +00:00
ar71xx_machdep.c	Populate hw.model with the CPU model information.	2015-07-14 05:14:10 +00:00
ar71xx_ohci.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_pci_bus_space.c
ar71xx_pci_bus_space.h
ar71xx_pci.c	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
ar71xx_setup.c	Add initial Qualcomm Atheros QCA955x SoC support.	2015-01-05 02:06:26 +00:00
ar71xx_setup.h	add QCA955x SoC types.	2015-01-05 01:59:44 +00:00
ar71xx_spi.c
ar71xx_wdog.c
ar71xxreg.h	Add a MII mode for SGMII.	2015-03-02 01:23:59 +00:00
ar91xx_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar91xx_chip.h
ar91xxreg.h
ar724x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar724x_chip.h
ar724x_pci.c	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
ar724xreg.h	Note that the AR724x PCIe registers are actually from the PCI_CTRL	2015-03-21 05:59:45 +00:00
ar933x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar933x_chip.h
ar933x_uart.h
ar933xreg.h
ar934x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar934x_chip.h
ar934x_nfcreg.h	Add the AR934x NAND flash controller register definitions.	2014-03-18 12:18:35 +00:00
ar934xreg.h	Add AR934x specific GPIO functions and output MUX configuration.	2015-01-03 06:35:53 +00:00
files.ar71xx	Add initial support for the QCA955x PCIe host controller.	2015-05-19 05:31:58 +00:00
if_arge.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
if_argevar.h	The linux driver code for the MDIO bus does a read-after-write	2015-02-02 17:33:00 +00:00
pcf2123_rtc.c
pcf2123reg.h
qca955x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
qca955x_chip.h	Add initial Qualcomm Atheros QCA955x SoC support.	2015-01-05 02:06:26 +00:00
qca955x_pci.c	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
qca955xreg.h	Oops - fix typo.	2015-07-03 07:00:24 +00:00
std.ar71xx
uart_bus_ar71xx.c
uart_bus_ar933x.c
uart_cpu_ar71xx.c
uart_cpu_ar933x.c
uart_dev_ar933x.c	Add support for the uart classes to set their default register shift value.	2015-04-11 17:16:23 +00:00
uart_dev_ar933x.h