54a8c69347
Interrupts under the new scheme are managed by the i386 nexus with the awareness of the resource manager. There is further room for optimizing the interfaces still. All the users of register_intr()/intr_create() should be gone, with the exception of pcic and i386/isa/clock.c.
791 lines
24 KiB
C
791 lines
24 KiB
C
/*-
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* Copyright (c) 1998, 1999 Takanori Watanabe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: intpm.c,v 1.4 1999/01/28 00:57:53 dillon Exp $
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*/
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#include "pci.h"
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#include "intpm.h"
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#if NPCI > 0
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#if NINTPM >0
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/* I don't think the chip is used in other architecture. :-)*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <machine/bus_pio.h>
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#include <machine/bus_memio.h>
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#include <machine/bus.h>
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#include <machine/clock.h>
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#include <sys/uio.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <dev/smbus/smbconf.h>
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#include "smbus_if.h"
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/*This should be removed if force_pci_map_int supported*/
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#include <sys/interrupt.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/intpmreg.h>
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#include "opt_intpm.h"
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static struct _pcsid
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{
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pcidi_t type;
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char *desc;
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} pci_ids[] =
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{
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{ 0x71138086,"Intel 82371AB Power management controller"},
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{ 0x00000000, NULL }
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};
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static int intsmb_probe(device_t);
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static int intsmb_attach(device_t);
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static void intsmb_print_child(device_t, device_t);
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static int intsmb_intr(device_t dev);
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static int intsmb_slvintr(device_t dev);
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static void intsmb_alrintr(device_t dev);
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static int intsmb_callback(device_t dev, int index, caddr_t data);
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static int intsmb_quick(device_t dev, u_char slave, int how);
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static int intsmb_sendb(device_t dev, u_char slave, char byte);
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static int intsmb_recvb(device_t dev, u_char slave, char *byte);
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static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
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static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
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static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
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static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
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static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
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static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
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static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char count, char *buf);
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static void intsmb_start(device_t dev,u_char cmd,int nointr);
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static int intsmb_stop(device_t dev);
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static int intsmb_stop_poll(device_t dev);
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static int intsmb_free(device_t dev);
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static struct intpm_pci_softc *intpm_alloc(int unit);
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static const char* intpm_probe __P((pcici_t tag, pcidi_t type));
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static void intpm_attach __P((pcici_t config_id, int unit));
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static devclass_t intsmb_devclass;
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static device_method_t intpm_methods[]={
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DEVMETHOD(device_probe,intsmb_probe),
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DEVMETHOD(device_attach,intsmb_attach),
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DEVMETHOD(bus_print_child, intsmb_print_child),
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DEVMETHOD(smbus_callback,intsmb_callback),
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DEVMETHOD(smbus_quick,intsmb_quick),
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DEVMETHOD(smbus_sendb,intsmb_sendb),
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DEVMETHOD(smbus_recvb,intsmb_recvb),
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DEVMETHOD(smbus_writeb,intsmb_writeb),
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DEVMETHOD(smbus_writew,intsmb_writew),
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DEVMETHOD(smbus_readb,intsmb_readb),
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DEVMETHOD(smbus_readw,intsmb_readw),
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DEVMETHOD(smbus_pcall,intsmb_pcall),
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DEVMETHOD(smbus_bwrite,intsmb_bwrite),
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DEVMETHOD(smbus_bread,intsmb_bread),
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{0,0}
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};
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static struct intpm_pci_softc{
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bus_space_tag_t smbst;
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bus_space_handle_t smbsh;
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bus_space_tag_t pmst;
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bus_space_handle_t pmsh;
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pcici_t cfg;
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device_t smbus;
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}intpm_pci[NINTPM];
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struct intsmb_softc{
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struct intpm_pci_softc *pci_sc;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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device_t smbus;
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int isbusy;
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};
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static driver_t intpm_driver = {
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"intsmb",
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intpm_methods,
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DRIVER_TYPE_MISC,
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sizeof(struct intsmb_softc),
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};
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static u_long intpm_count ;
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static struct pci_device intpm_device = {
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"intpm",
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intpm_probe,
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intpm_attach,
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&intpm_count
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};
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DATA_SET (pcidevice_set, intpm_device);
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static int
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intsmb_probe(device_t dev)
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{
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struct intsmb_softc *sc =(struct intsmb_softc *) device_get_softc(dev);
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sc->smbus=smbus_alloc_bus(dev);
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if (!sc->smbus)
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return (EINVAL); /* XXX don't know what to return else */
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device_set_desc(dev,"Intel PIIX4 SMBUS Interface");
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return (0); /* XXX don't know what to return else */
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}
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static int
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intsmb_attach(device_t dev)
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{
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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sc->pci_sc=&intpm_pci[device_get_unit(dev)];
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sc->isbusy=0;
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sc->sh=sc->pci_sc->smbsh;
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sc->st=sc->pci_sc->smbst;
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sc->pci_sc->smbus=dev;
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device_probe_and_attach(sc->smbus);
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#ifdef ENABLE_ALART
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/*Enable Arart*/
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBSLVCNT,
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PIIX4_SMBSLVCNT_ALTEN);
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#endif
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return (0);
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}
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static void
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intsmb_print_child(device_t bus, device_t dev)
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{
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printf(" on %s%d", device_get_name(bus), device_get_unit(bus));
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return;
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}
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static int
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intsmb_callback(device_t dev, int index, caddr_t data)
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{
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int error = 0;
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intrmask_t s;
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s=splnet();
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switch (index) {
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case SMB_REQUEST_BUS:
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break;
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case SMB_RELEASE_BUS:
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break;
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default:
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error = EINVAL;
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}
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splx(s);
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return (error);
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}
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/*counterpart of smbtx_smb_free*/
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static int
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intsmb_free(device_t dev){
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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if((bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTSTS)&
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PIIX4_SMBHSTSTAT_BUSY)
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#ifdef ENABLE_ALART
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||(bus_space_read_1(sc->st,sc->sh,PIIX4_SMBSLVSTS)&
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PIIX4_SMBSLVSTS_BUSY)
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#endif
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|| sc->isbusy)
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return EBUSY;
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sc->isbusy=1;
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/*Disable Intrrupt in slave part*/
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#ifndef ENABLE_ALART
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBSLVCNT,0);
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#endif
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/*Reset INTR Flag to prepare INTR*/
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTSTS,
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(PIIX4_SMBHSTSTAT_INTR|
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PIIX4_SMBHSTSTAT_ERR|
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PIIX4_SMBHSTSTAT_BUSC|
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PIIX4_SMBHSTSTAT_FAIL)
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);
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return 0;
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}
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static int
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intsmb_intr(device_t dev)
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{
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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int status;
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intrmask_t s;
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status=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTSTS);
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if(status&PIIX4_SMBHSTSTAT_BUSY){
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return 1;
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}
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s=splhigh();
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if(sc->isbusy&&(status&(PIIX4_SMBHSTSTAT_INTR|
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PIIX4_SMBHSTSTAT_ERR|
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PIIX4_SMBHSTSTAT_BUSC|
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PIIX4_SMBHSTSTAT_FAIL))){
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int tmp;
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sc->isbusy=0;
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tmp=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTCNT);
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCNT,
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tmp&~PIIX4_SMBHSTCNT_INTREN);
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splx(s);
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wakeup(sc);
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return 0;
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}
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splx(s);
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return 1;/* Not Completed*/
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}
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static int
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intsmb_slvintr(device_t dev)
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{
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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int status,retval;
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retval=1;
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status=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBSLVSTS);
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if(status&PIIX4_SMBSLVSTS_BUSY)
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return retval;
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if(status&PIIX4_SMBSLVSTS_ALART){
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intsmb_alrintr(dev);
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retval=0;
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}else if(status&~(PIIX4_SMBSLVSTS_ALART|PIIX4_SMBSLVSTS_SDW2
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|PIIX4_SMBSLVSTS_SDW1)){
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retval=0;
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}
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/*Reset Status Register*/
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBSLVSTS,PIIX4_SMBSLVSTS_ALART|
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PIIX4_SMBSLVSTS_SDW2|PIIX4_SMBSLVSTS_SDW1|
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PIIX4_SMBSLVSTS_SLV);
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return retval;
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}
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static void intsmb_alrintr(device_t dev)
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{
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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int slvcnt;
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#ifdef ENABLE_ALART
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int error;
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#endif
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/*stop generating INTR from ALART*/
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slvcnt=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBSLVCNT);
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#ifdef ENABLE_ALART
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBSLVCNT,
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slvcnt&~PIIX4_SMBSLVCNT_ALTEN) ;
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#endif
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DELAY(5);
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/*ask bus who assert it and then ask it what's the matter. */
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#ifdef ENABLE_ALART
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error=intsmb_free(dev);
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if(!error){
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,SMBALTRESP
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|LSB);
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intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BYTE,1);
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if(!(error=intsmb_stop_poll(dev))){
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volatile u_int8_t *addr;
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addr=bus_space_read_1(sc->st,sc->sh,
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PIIX4_SMBHSTDAT0);
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printf("ALART_RESPONSE: %p\n", addr);
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}
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}else{
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printf("ERROR\n");
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}
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/*Re-enable INTR from ALART*/
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBSLVCNT,
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slvcnt|PIIX4_SMBSLVCNT_ALTEN) ;
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DELAY(5);
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#endif
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return;
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}
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static void
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intsmb_start(device_t dev,unsigned char cmd,int nointr)
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{
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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unsigned char tmp;
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tmp=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTCNT);
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tmp&= 0xe0;
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tmp |= cmd;
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tmp |=PIIX4_SMBHSTCNT_START;
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/*While not in autoconfiguration Intrrupt Enabled*/
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if(!cold||!nointr)
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tmp |=PIIX4_SMBHSTCNT_INTREN;
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCNT,tmp);
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}
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/*Polling Code. Polling is not encouraged
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* because It is required to wait for the device get busy.
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*(29063505.pdf from Intel)
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* But during boot,intrrupt cannot be used.
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* so use polling code while in autoconfiguration.
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*/
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static int
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intsmb_stop_poll(device_t dev){
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int error,i;
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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/*
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* In smbtx driver ,Simply waiting.
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* This loops 100-200 times.
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*/
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for(i=0;i<0x7fff;i++){
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if((bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTSTS)
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&PIIX4_SMBHSTSTAT_BUSY)){
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break;
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}
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}
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for(i=0;i<0x7fff;i++){
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int status;
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status=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTSTS);
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if(!(status&PIIX4_SMBHSTSTAT_BUSY)){
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sc->isbusy=0;
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error=(status&PIIX4_SMBHSTSTAT_ERR)?EIO :
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(status&PIIX4_SMBHSTSTAT_BUSC)?EBUSY:
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(status&PIIX4_SMBHSTSTAT_FAIL)?EIO:0;
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if(error==0&&!(status&PIIX4_SMBHSTSTAT_INTR)){
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printf("unknown cause why?");
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}
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return error;
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}
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}
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sc->isbusy=0;
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return EIO;
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}
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/*
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*wait for completion and return result.
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*/
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static int
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intsmb_stop(device_t dev){
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int error;
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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if(cold){
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/*So that it can use device during probing device on SMBus.*/
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error=intsmb_stop_poll(dev);
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return error;
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}else{
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if(!tsleep(sc,(PWAIT)|PCATCH,"SMBWAI",hz/8)){
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int status;
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status=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTSTS);
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if(!(status&PIIX4_SMBHSTSTAT_BUSY)){
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error=(status&PIIX4_SMBHSTSTAT_ERR)?EIO :
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(status&PIIX4_SMBHSTSTAT_BUSC)?EBUSY:
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(status&PIIX4_SMBHSTSTAT_FAIL)?EIO:0;
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if(error==0&&!(status&PIIX4_SMBHSTSTAT_INTR)){
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printf("intsmb%d:unknown cause why?\n",
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device_get_unit(dev));
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}
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#ifdef ENABLE_ALART
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bus_space_write_1(sc->st,sc->sh,
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PIIX4_SMBSLVCNT,PIIX4_SMBSLVCNT_ALTEN);
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#endif
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return error;
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}
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}
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}
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/*Timeout Procedure*/
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sc->isbusy=0;
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/*Re-enable supressed intrrupt from slave part*/
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bus_space_write_1(sc->st,sc->sh,
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PIIX4_SMBSLVCNT,PIIX4_SMBSLVCNT_ALTEN);
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return EIO;
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}
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static int
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intsmb_quick(device_t dev, u_char slave, int how)
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{
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int error=0;
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u_char data;
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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data=slave;
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/*Quick command is part of Address, I think*/
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switch(how){
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case SMB_QWRITE:
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data&=~LSB;
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break;
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case SMB_QREAD:
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data|=LSB;
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break;
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default:
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error=EINVAL;
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}
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if(!error){
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error=intsmb_free(dev);
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if(!error){
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bus_space_write_1(sc->st,sc->sh,
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PIIX4_SMBHSTADD,data);
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intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_QUICK,0);
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error=intsmb_stop(dev);
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}
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}
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return (error);
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}
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static int
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intsmb_sendb(device_t dev, u_char slave, char byte)
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{
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int error;
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struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
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error=intsmb_free(dev);
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if(!error){
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave&~LSB);
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bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,byte);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BYTE,0);
|
|
error=intsmb_stop(dev);
|
|
}
|
|
return (error);
|
|
}
|
|
static int
|
|
intsmb_recvb(device_t dev, u_char slave, char *byte)
|
|
{
|
|
int error;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(!error){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave
|
|
|LSB);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BYTE,0);
|
|
if(!(error=intsmb_stop(dev))){
|
|
#ifdef RECV_IS_IN_CMD
|
|
/*Linux SMBus stuff also troubles
|
|
Because Intel's datasheet will not make clear.
|
|
*/
|
|
*byte=bus_space_read_1(sc->st,sc->sh,
|
|
PIIX4_SMBHSTCMD);
|
|
#else
|
|
*byte=bus_space_read_1(sc->st,sc->sh,
|
|
PIIX4_SMBHSTDAT0);
|
|
#endif
|
|
}
|
|
}
|
|
return (error);
|
|
}
|
|
static int
|
|
intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
|
|
{
|
|
int error;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(!error){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave&~LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0,byte);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BDATA,0);
|
|
error=intsmb_stop(dev);
|
|
}
|
|
return (error);
|
|
}
|
|
static int
|
|
intsmb_writew(device_t dev, u_char slave, char cmd, short word)
|
|
{
|
|
int error;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(!error){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave&~LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0,
|
|
word&0xff);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT1,
|
|
(word>>8)&0xff);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_WDATA,0);
|
|
error=intsmb_stop(dev);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
|
|
{
|
|
int error;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(!error){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave|LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BDATA,0);
|
|
if(!(error=intsmb_stop(dev))){
|
|
*byte=bus_space_read_1(sc->st,sc->sh,
|
|
PIIX4_SMBHSTDAT0);
|
|
}
|
|
}
|
|
return (error);
|
|
}
|
|
static int
|
|
intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
|
|
{
|
|
int error;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(!error){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave|LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_WDATA,0);
|
|
if(!(error=intsmb_stop(dev))){
|
|
*word=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0)&0xff;
|
|
*word|=(bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTDAT1)&0xff)<<8;
|
|
}
|
|
}
|
|
return (error);
|
|
}
|
|
/*
|
|
* Data sheet claims that it implements all function, but also claims
|
|
* that it implements 7 function and not mention PCALL. So I don't know
|
|
* whether it will work.
|
|
*/
|
|
static int
|
|
intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
|
|
{
|
|
#ifdef PROCCALL_TEST
|
|
int error;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(!error){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave&~LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0,sdata&0xff);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT1,(sdata&0xff)>>8);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_WDATA,0);
|
|
}
|
|
if(!(error=intsmb_stop(dev))){
|
|
*rdata=bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0)&0xff;
|
|
*rdata|=(bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTDAT1)&0xff)<<8;
|
|
}
|
|
return error;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
static int
|
|
intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
|
|
{
|
|
int error,i;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(count>SMBBLOCKTRANS_MAX||count==0)
|
|
error=EINVAL;
|
|
if(!error){
|
|
/*Reset internal array index*/
|
|
bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTCNT);
|
|
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave&~LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
for(i=0;i<count;i++){
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBBLKDAT,buf[i]);
|
|
}
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0,count);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BLOCK,0);
|
|
error=intsmb_stop(dev);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
intsmb_bread(device_t dev, u_char slave, char cmd, u_char count, char *buf)
|
|
{
|
|
int error,i;
|
|
struct intsmb_softc *sc = (struct intsmb_softc *)device_get_softc(dev);
|
|
error=intsmb_free(dev);
|
|
if(count>SMBBLOCKTRANS_MAX||count==0)
|
|
error=EINVAL;
|
|
if(!error){
|
|
/*Reset internal array index*/
|
|
bus_space_read_1(sc->st,sc->sh,PIIX4_SMBHSTCNT);
|
|
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTADD,slave|LSB);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTCMD,cmd);
|
|
bus_space_write_1(sc->st,sc->sh,PIIX4_SMBHSTDAT0,count);
|
|
intsmb_start(dev,PIIX4_SMBHSTCNT_PROT_BLOCK,0);
|
|
error=intsmb_stop(dev);
|
|
if(!error){
|
|
bzero(buf,count);/*Is it needed?*/
|
|
count= bus_space_read_1(sc->st,sc->sh,
|
|
PIIX4_SMBHSTDAT0);
|
|
if(count!=0&&count<=SMBBLOCKTRANS_MAX){
|
|
for(i=0;i<count;i++){
|
|
buf[i]=bus_space_read_1(sc->st,
|
|
sc->sh,
|
|
PIIX4_SMBBLKDAT);
|
|
}
|
|
}
|
|
else{
|
|
error=EIO;
|
|
}
|
|
}
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
DRIVER_MODULE(intsmb, root , intpm_driver, intsmb_devclass, 0, 0);
|
|
|
|
|
|
static void intpm_intr __P((void *arg));
|
|
|
|
static const char*
|
|
intpm_probe (pcici_t tag, pcidi_t type)
|
|
{
|
|
struct _pcsid *ep =pci_ids;
|
|
while (ep->type && ep->type != type)
|
|
++ep;
|
|
return (ep->desc);
|
|
}
|
|
|
|
static struct intpm_pci_softc *intpm_alloc(int unit){
|
|
if(unit<NINTPM)
|
|
return &intpm_pci[unit];
|
|
else
|
|
return NULL;
|
|
}
|
|
|
|
/*Same as pci_map_int but this ignores INTPIN*/
|
|
static int force_pci_map_int(pcici_t cfg, pci_inthand_t *func, void *arg, unsigned *maskptr)
|
|
{
|
|
int error;
|
|
#ifdef APIC_IO
|
|
int nextpin, muxcnt;
|
|
#endif
|
|
/* Spec sheet claims that it use IRQ 9*/
|
|
int irq = 9;
|
|
void *idesc;
|
|
|
|
idesc = inthand_add(NULL, irq, func, arg, maskptr, 0);
|
|
if (idesc == 0)
|
|
return 0;
|
|
#ifdef APIC_IO
|
|
nextpin = next_apic_irq(irq);
|
|
|
|
if (nextpin < 0)
|
|
return 1;
|
|
|
|
/*
|
|
* Attempt handling of some broken mp tables.
|
|
*
|
|
* It's OK to yell (since the mp tables are broken).
|
|
*
|
|
* Hanging in the boot is not OK
|
|
*/
|
|
|
|
muxcnt = 2;
|
|
nextpin = next_apic_irq(nextpin);
|
|
while (muxcnt < 5 && nextpin >= 0) {
|
|
muxcnt++;
|
|
nextpin = next_apic_irq(nextpin);
|
|
}
|
|
if (muxcnt >= 5) {
|
|
printf("bogus MP table, more than 4 IO APIC pins connected to the same PCI device or ISA/EISA interrupt\n");
|
|
return 0;
|
|
}
|
|
|
|
printf("bogus MP table, %d IO APIC pins connected to the same PCI device or ISA/EISA interrupt\n", muxcnt);
|
|
|
|
nextpin = next_apic_irq(irq);
|
|
while (nextpin >= 0) {
|
|
idesc = inthand_add(NULL, nextpin, func, arg, maskptr, 0);
|
|
if (error != 0)
|
|
return 0;
|
|
printf("Registered extra interrupt handler for int %d (in addition to int %d)\n", nextpin, irq);
|
|
nextpin = next_apic_irq(nextpin);
|
|
}
|
|
#endif
|
|
return 1;
|
|
}
|
|
static void
|
|
intpm_attach(config_id, unit)
|
|
pcici_t config_id;
|
|
int unit;
|
|
{
|
|
int value;
|
|
|
|
char * str;
|
|
{
|
|
struct intpm_pci_softc *sciic;
|
|
device_t smbinterface;
|
|
value=pci_cfgread(config_id,PCI_BASE_ADDR_SMB,4);
|
|
sciic=intpm_alloc(unit);
|
|
if(sciic==NULL){
|
|
return;
|
|
}
|
|
|
|
sciic->smbst=(value&1)?I386_BUS_SPACE_IO:I386_BUS_SPACE_MEM;
|
|
|
|
/*Calling pci_map_port is better.But bus_space_handle_t !=
|
|
* pci_port_t, so I don't call support routine while
|
|
* bus_space_??? support routine will be appear.
|
|
*/
|
|
sciic->smbsh=value&(~1);
|
|
if(sciic->smbsh==I386_BUS_SPACE_MEM){
|
|
/*According to the spec, this will not occur*/
|
|
int dummy;
|
|
pci_map_mem(config_id,PCI_BASE_ADDR_SMB,&sciic->smbsh,&dummy);
|
|
}
|
|
printf("intpm%d: %s %x ",unit,
|
|
(sciic->smbst==I386_BUS_SPACE_IO)?"I/O mapped":"Memory",
|
|
sciic->smbsh);
|
|
#ifndef NO_CHANGE_PCICONF
|
|
pci_cfgwrite(config_id,PCIR_INTLINE,0x09,1);
|
|
pci_cfgwrite(config_id,PCI_HST_CFG_SMB,
|
|
PCI_INTR_SMB_IRQ9|PCI_INTR_SMB_ENABLE,1);
|
|
#endif
|
|
config_id->intline=pci_cfgread(config_id,PCIR_INTLINE,1);
|
|
printf("ALLOCED IRQ %d ",config_id->intline);
|
|
value=pci_cfgread(config_id,PCI_HST_CFG_SMB,1);
|
|
switch(value&0xe){
|
|
case PCI_INTR_SMB_SMI:
|
|
str="SMI";
|
|
break;
|
|
case PCI_INTR_SMB_IRQ9:
|
|
str="IRQ 9";
|
|
break;
|
|
default:
|
|
str="BOGUS";
|
|
}
|
|
printf("intr %s %s ",str,((value&1)? "enabled":"disabled"));
|
|
value=pci_cfgread(config_id,PCI_REVID_SMB,1);
|
|
printf("revision %d\n",value);
|
|
/*
|
|
* Install intr HANDLER here
|
|
*/
|
|
if(force_pci_map_int(config_id,intpm_intr,sciic,&net_imask)==0){
|
|
printf("intpm%d: Failed to map intr\n",unit);
|
|
}
|
|
smbinterface=device_add_child(root_bus,"intsmb",unit,NULL);
|
|
device_probe_and_attach(smbinterface);
|
|
}
|
|
value=pci_cfgread(config_id,PCI_BASE_ADDR_PM,4);
|
|
printf("intpm%d: PM %s %x \n",unit,(value&1)?"I/O mapped":"Memory",value&0xfffe);
|
|
return;
|
|
}
|
|
static void intpm_intr(void *arg)
|
|
{
|
|
struct intpm_pci_softc *sc;
|
|
sc=(struct intpm_pci_softc *)arg;
|
|
intsmb_intr(sc->smbus);
|
|
intsmb_slvintr(sc->smbus);
|
|
}
|
|
#endif /* NPCI > 0 */
|
|
#endif
|