148 lines
4.9 KiB
C
148 lines
4.9 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Module to support operations on core such as TLB config, etc.
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*
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* <hr>$Revision: 41586 $<hr>
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*
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*/
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-core.h"
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/**
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* Adds a wired TLB entry, and returns the index of the entry added.
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* Parameters are written to TLB registers without further processing.
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*
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* @param hi HI register value
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* @param lo0 lo0 register value
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* @param lo1 lo1 register value
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* @param page_mask pagemask register value
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*
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* @return Success: TLB index used (0-31) or (0-63) for OCTEON Plus
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* Failure: -1
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*/
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int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask)
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{
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uint32_t index;
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uint32_t index_limit = 31;
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if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
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{
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index_limit=63;
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}
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CVMX_MF_TLB_WIRED(index);
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if (index >= index_limit)
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{
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return(-1);
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}
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CVMX_MT_ENTRY_HIGH(hi);
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CVMX_MT_ENTRY_LO_0(lo0);
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CVMX_MT_ENTRY_LO_1(lo1);
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CVMX_MT_PAGEMASK(page_mask);
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CVMX_MT_TLB_INDEX(index);
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CVMX_MT_TLB_WIRED(index + 1);
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CVMX_EHB;
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CVMX_TLBWI;
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CVMX_EHB;
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return(index);
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}
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/**
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* Adds a fixed (wired) TLB mapping. Returns TLB index used or -1 on error.
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* This is a wrapper around cvmx_core_add_wired_tlb_entry()
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*
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* @param vaddr Virtual address to map
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* @param page0_addr page 0 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
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* @param page1_addr page1 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
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* @param page_mask page mask.
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*
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* @return Success: TLB index used (0-31)
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* Failure: -1
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*/
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int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
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{
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if ((vaddr & (page_mask | 0x7ff))
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|| ((page0_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1))
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|| ((page1_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1)))
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{
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cvmx_dprintf("Error adding tlb mapping: invalid address alignment at vaddr: 0x%llx\n", (unsigned long long)vaddr);
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return(-1);
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}
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return(cvmx_core_add_wired_tlb_entry(vaddr,
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(page0_addr >> 6) | (page0_addr & 0x7),
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(page1_addr >> 6) | (page1_addr & 0x7),
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page_mask));
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}
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/**
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* Adds a fixed (wired) TLB mapping. Returns TLB index used or -1 on error.
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* Assumes both pages are valid. Use cvmx_core_add_fixed_tlb_mapping_bits for more control.
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* This is a wrapper around cvmx_core_add_wired_tlb_entry()
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*
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* @param vaddr Virtual address to map
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* @param page0_addr page 0 physical address
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* @param page1_addr page1 physical address
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* @param page_mask page mask.
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*
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* @return Success: TLB index used (0-31)
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* Failure: -1
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*/
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int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
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{
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return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask));
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}
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