400 lines
12 KiB
C
400 lines
12 KiB
C
/*
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* Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the acknowledgement as bellow:
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*
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* This product includes software developed by K. Kobayashi and H. Shimokawa
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*
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#define PCI_CBMEM 0x10
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#define FW_VENDORID_NEC 0x1033
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#define FW_VENDORID_TI 0x104c
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#define FW_VENDORID_SONY 0x104d
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#define FW_VENDORID_VIA 0x1106
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#define FW_VENDORID_RICOH 0x1180
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#define FW_VENDORID_APPLE 0x106b
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#define FW_VENDORID_LUCENT 0x11c1
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#define FW_DEVICE_UPD861 0x0063
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#define FW_DEVICE_TITSB22 0x8009
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#define FW_DEVICE_TITSB23 0x8019
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#define FW_DEVICE_TITSB26 0x8020
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#define FW_DEVICE_TITSB43 0x8021
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#define FW_DEVICE_CX3022 0x8039
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#define FW_DEVICE_VT6306 0x3044
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#define FW_DEVICE_R5C552 0x1180
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#define FW_DEVICE_PANGEA 0x0030
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#define FW_DEVICE_UNINORTH 0x0031
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#define FW_DEVICE_FW322 0x5811
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#define PCI_INTERFACE_OHCI 0x10
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#define FW_OHCI_BASE_REG 0x10
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#define OHCI_DMA_ITCH 0x20
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#define OHCI_DMA_IRCH 0x20
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#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
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typedef volatile u_int32_t fwohcireg_t;
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struct fwohcidb {
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union {
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struct {
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volatile u_int32_t cmd;
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volatile u_int32_t addr;
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volatile u_int32_t depend;
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volatile u_int32_t count:16,
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status:16;
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} desc;
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volatile u_int32_t immed[4];
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} db;
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#define OHCI_OUTPUT_MORE (0 << 28)
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#define OHCI_OUTPUT_LAST (1 << 28)
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#define OHCI_INPUT_MORE (2 << 28)
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#define OHCI_INPUT_LAST (3 << 28)
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#define OHCI_STORE_QUAD (4 << 28)
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#define OHCI_LOAD_QUAD (5 << 28)
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#define OHCI_NOP (6 << 28)
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#define OHCI_STOP (7 << 28)
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#define OHCI_STORE (8 << 28)
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#define OHCI_CMD_MASK (0xf << 28)
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#define OHCI_UPDATE (1 << 27)
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#define OHCI_KEY_ST0 (0 << 24)
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#define OHCI_KEY_ST1 (1 << 24)
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#define OHCI_KEY_ST2 (2 << 24)
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#define OHCI_KEY_ST3 (3 << 24)
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#define OHCI_KEY_REGS (5 << 24)
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#define OHCI_KEY_SYS (6 << 24)
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#define OHCI_KEY_DEVICE (7 << 24)
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#define OHCI_KEY_MASK (7 << 24)
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#define OHCI_INTERRUPT_NEVER (0 << 20)
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#define OHCI_INTERRUPT_TRUE (1 << 20)
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#define OHCI_INTERRUPT_FALSE (2 << 20)
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#define OHCI_INTERRUPT_ALWAYS (3 << 20)
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#define OHCI_BRANCH_NEVER (0 << 18)
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#define OHCI_BRANCH_TRUE (1 << 18)
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#define OHCI_BRANCH_FALSE (2 << 18)
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#define OHCI_BRANCH_ALWAYS (3 << 18)
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#define OHCI_BRANCH_MASK (3 << 18)
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#define OHCI_WAIT_NEVER (0 << 16)
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#define OHCI_WAIT_TRUE (1 << 16)
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#define OHCI_WAIT_FALSE (2 << 16)
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#define OHCI_WAIT_ALWAYS (3 << 16)
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};
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#define OHCI_SPD_S100 0x4
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#define OHCI_SPD_S200 0x1
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#define OHCI_SPD_S400 0x2
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#define FWOHCIEV_NOSTAT 0
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#define FWOHCIEV_LONGP 2
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#define FWOHCIEV_MISSACK 3
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#define FWOHCIEV_UNDRRUN 4
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#define FWOHCIEV_OVRRUN 5
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#define FWOHCIEV_DESCERR 6
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#define FWOHCIEV_DTRDERR 7
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#define FWOHCIEV_DTWRERR 8
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#define FWOHCIEV_BUSRST 9
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#define FWOHCIEV_TIMEOUT 0xa
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#define FWOHCIEV_TCODERR 0xb
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#define FWOHCIEV_UNKNOWN 0xe
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#define FWOHCIEV_FLUSHED 0xf
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#define FWOHCIEV_ACKCOMPL 0x11
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#define FWOHCIEV_ACKPEND 0x12
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#define FWOHCIEV_ACKBSX 0x14
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#define FWOHCIEV_ACKBSA 0x15
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#define FWOHCIEV_ACKBSB 0x16
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#define FWOHCIEV_ACKTARD 0x1b
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#define FWOHCIEV_ACKDERR 0x1d
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#define FWOHCIEV_ACKTERR 0x1e
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#define FWOHCIEV_MASK 0x1f
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struct ohci_registers {
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fwohcireg_t ver; /* Version No. 0x0 */
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fwohcireg_t guid; /* GUID_ROM No. 0x4 */
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fwohcireg_t retry; /* AT retries 0x8 */
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#define FWOHCI_RETRY 0x8
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fwohcireg_t csr_data; /* CSR data 0xc */
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fwohcireg_t csr_cmp; /* CSR compare 0x10 */
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fwohcireg_t csr_cntl; /* CSR compare 0x14 */
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fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */
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fwohcireg_t bus_id; /* BUS_ID 0x1c */
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fwohcireg_t bus_opt; /* BUS option 0x20 */
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#define FWOHCIGUID_H 0x24
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#define FWOHCIGUID_L 0x28
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fwohcireg_t guid_hi; /* GUID hi 0x24 */
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fwohcireg_t guid_lo; /* GUID lo 0x28 */
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fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
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fwohcireg_t config_rom; /* config ROM map 0x34 */
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fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
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fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
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fwohcireg_t vender; /* vender ID 0x40 */
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fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
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fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
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fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
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#define OHCI_HCC_BIGEND (1 << 30)
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#define OHCI_HCC_PRPHY (1 << 23)
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#define OHCI_HCC_PHYEN (1 << 22)
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#define OHCI_HCC_LPS (1 << 19)
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#define OHCI_HCC_POSTWR (1 << 18)
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#define OHCI_HCC_LINKEN (1 << 17)
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#define OHCI_HCC_RESET (1 << 16)
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fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */
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fwohcireg_t dummy3[1]; /* dummy 0x60 */
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fwohcireg_t sid_buf; /* self id buffer 0x64 */
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fwohcireg_t sid_cnt; /* self id count 0x68 */
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fwohcireg_t dummy4[1]; /* dummy 0x6c */
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fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */
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fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */
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fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */
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fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */
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#define FWOHCI_INTSTAT 0x80
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#define FWOHCI_INTSTATCLR 0x84
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#define FWOHCI_INTMASK 0x88
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#define FWOHCI_INTMASKCLR 0x8c
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fwohcireg_t int_stat; /* 0x80 */
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fwohcireg_t int_clear; /* 0x84 */
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fwohcireg_t int_mask; /* 0x88 */
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fwohcireg_t int_mask_clear; /* 0x8c */
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fwohcireg_t it_int_stat; /* 0x90 */
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fwohcireg_t it_int_clear; /* 0x94 */
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fwohcireg_t it_int_mask; /* 0x98 */
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fwohcireg_t it_mask_clear; /* 0x9c */
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fwohcireg_t ir_int_stat; /* 0xa0 */
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fwohcireg_t ir_int_clear; /* 0xa4 */
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fwohcireg_t ir_int_mask; /* 0xa8 */
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fwohcireg_t ir_mask_clear; /* 0xac */
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fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */
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fwohcireg_t fairness; /* fairness control 0xdc */
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fwohcireg_t link_cntl; /* Chip control 0xe0*/
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fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
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#define FWOHCI_NODEID 0xe8
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fwohcireg_t node; /* Node ID 0xe8 */
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#define OHCI_NODE_VALID (1 << 31)
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#define OHCI_NODE_ROOT (1 << 30)
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#define OHCI_ASYSRCBUS 1
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fwohcireg_t phy_access; /* PHY cntl 0xec */
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#define PHYDEV_RDDONE (1<<31)
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#define PHYDEV_RDCMD (1<<15)
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#define PHYDEV_WRCMD (1<<14)
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#define PHYDEV_REGADDR 8
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#define PHYDEV_WRDATA 0
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#define PHYDEV_RDADDR 24
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#define PHYDEV_RDDATA 16
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fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */
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fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */
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fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */
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fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */
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fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */
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fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */
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fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
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fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
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fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
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fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
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fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
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fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
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struct ohci_dma{
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fwohcireg_t cntl;
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#define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
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#define OHCI_CNTL_BUFFIL (0x1 << 31)
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#define OHCI_CNTL_ISOHDR (0x1 << 30)
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#define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
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#define OHCI_CNTL_MULTICH (0x1 << 28)
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#define OHCI_CNTL_DMA_RUN (0x1 << 15)
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#define OHCI_CNTL_DMA_WAKE (0x1 << 12)
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#define OHCI_CNTL_DMA_DEAD (0x1 << 11)
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#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10)
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#define OHCI_CNTL_DMA_BT (0x1 << 8)
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#define OHCI_CNTL_DMA_BAD (0x1 << 7)
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#define OHCI_CNTL_DMA_STAT (0xff)
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fwohcireg_t cntl_clr;
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fwohcireg_t dummy0;
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fwohcireg_t cmd;
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fwohcireg_t match;
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fwohcireg_t dummy1;
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fwohcireg_t dummy2;
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fwohcireg_t dummy3;
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};
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/* 0x180, 0x184, 0x188, 0x18c */
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/* 0x190, 0x194, 0x198, 0x19c */
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/* 0x1a0, 0x1a4, 0x1a8, 0x1ac */
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/* 0x1b0, 0x1b4, 0x1b8, 0x1bc */
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/* 0x1c0, 0x1c4, 0x1c8, 0x1cc */
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/* 0x1d0, 0x1d4, 0x1d8, 0x1dc */
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/* 0x1e0, 0x1e4, 0x1e8, 0x1ec */
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/* 0x1f0, 0x1f4, 0x1f8, 0x1fc */
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struct ohci_dma dma_ch[0x4];
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/* 0x200, 0x204, 0x208, 0x20c */
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/* 0x210, 0x204, 0x208, 0x20c */
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struct ohci_itdma{
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fwohcireg_t cntl;
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fwohcireg_t cntl_clr;
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fwohcireg_t dummy0;
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fwohcireg_t cmd;
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};
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struct ohci_itdma dma_itch[0x20];
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/* 0x400, 0x404, 0x408, 0x40c */
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/* 0x410, 0x404, 0x408, 0x40c */
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struct ohci_dma dma_irch[0x20];
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};
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struct fwohcidb_tr{
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STAILQ_ENTRY(fwohcidb_tr) link;
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struct fw_xfer *xfer;
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volatile struct fwohcidb *db;
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caddr_t buf;
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caddr_t dummy;
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int dbcnt;
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};
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/*
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* OHCI info structure.
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*/
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#if 0
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struct fwohci_softc {
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struct fw_softc fc;
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volatile struct ohci_registers *base;
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int init;
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#define SIDPHASE 1
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u_int32_t flags;
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struct fwohcidb_tr *db_tr[OHCI_MAX_DMA_CH];
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struct fwohcidb_tr *db_first[OHCI_MAX_DMA_CH];
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struct fwohcidb_tr *db_last[OHCI_MAX_DMA_CH];
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struct {
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int tail;
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struct fwohcidb_tr *db_tr;
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struct fwohcidb *db;
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}dbdvtx[MAX_DVFRAME], dbdvrx[MAX_DVFRAME];
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int ndb[OHCI_MAX_DMA_CH];
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u_int32_t isohdr[OHCI_MAX_DMA_CH];
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int queued[OHCI_MAX_DMA_CH];
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int dma_ch[OHCI_MAX_DMA_CH];
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};
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#endif
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struct fwohci_txpkthdr{
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union{
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u_int32_t ld[4];
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struct {
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u_int32_t res3:4,
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tcode:4,
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res2:8,
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spd:3,
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res1:13;
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}common;
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struct {
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u_int32_t res3:4,
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tcode:4,
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tlrt:8,
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spd:3,
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res2:4,
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srcbus:1,
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res1:8;
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u_int32_t res4:16,
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dst:16;
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}asycomm;
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struct {
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u_int32_t sy:4,
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tcode:4,
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chtag:8,
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spd:3,
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res1:13;
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u_int32_t res2:16,
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len:16;
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}stream;
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}mode;
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};
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struct fwohci_trailer{
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u_int32_t time:16,
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stat:16;
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};
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#define OHCI_CNTL_CYCSRC (0x1 << 22)
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#define OHCI_CNTL_CYCMTR (0x1 << 21)
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#define OHCI_CNTL_CYCTIMER (0x1 << 20)
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#define OHCI_CNTL_PHYPKT (0x1 << 10)
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#define OHCI_CNTL_SID (0x1 << 9)
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#define OHCI_INT_DMA_ATRQ (0x1 << 0)
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#define OHCI_INT_DMA_ATRS (0x1 << 1)
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#define OHCI_INT_DMA_ARRQ (0x1 << 2)
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#define OHCI_INT_DMA_ARRS (0x1 << 3)
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#define OHCI_INT_DMA_PRRQ (0x1 << 4)
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#define OHCI_INT_DMA_PRRS (0x1 << 5)
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#define OHCI_INT_DMA_IT (0x1 << 6)
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#define OHCI_INT_DMA_IR (0x1 << 7)
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#define OHCI_INT_PW_ERR (0x1 << 8)
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#define OHCI_INT_LR_ERR (0x1 << 9)
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#define OHCI_INT_PHY_SID (0x1 << 16)
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#define OHCI_INT_PHY_BUS_R (0x1 << 17)
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#define OHCI_INT_PHY_INT (0x1 << 19)
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#define OHCI_INT_CYC_START (0x1 << 20)
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#define OHCI_INT_CYC_64SECOND (0x1 << 21)
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#define OHCI_INT_CYC_LOST (0x1 << 22)
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#define OHCI_INT_CYC_ERR (0x1 << 23)
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#define OHCI_INT_ERR (0x1 << 24)
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#define OHCI_INT_CYC_LONG (0x1 << 25)
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#define OHCI_INT_PHY_REG (0x1 << 26)
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#define OHCI_INT_EN (0x1 << 31)
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#define IP_CHANNELS 0x0234
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#define FWOHCI_MAXREC 2048
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#define OHCI_ISORA 0x02
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#define OHCI_ISORB 0x04
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#define FWOHCITCODE_PHY 0xe
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