9c6d6488fa
we will import a newer version of the Linux code so the linuxkpi was not used. This is still missing 10G support, and multicast has not been tested. Reviewed by: gnn Obtained from: ABT Systems Ltd Sponsored by: SoftIron Inc Differential Revision: https://reviews.freebsd.org/D8549
890 lines
27 KiB
C
890 lines
27 KiB
C
/*
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* AMD 10Gb Ethernet driver
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*
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* This file is available to you under your choice of the following two
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* licenses:
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*
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* License 1: GPLv2
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*
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* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
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*
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* This file is free software; you may copy, redistribute and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or (at
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* your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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|
* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
|
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* annotated with this license and the Software, to deal in the Software
|
|
* without restriction, including without limitation the rights to use,
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|
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
|
|
* to do so, subject to the following conditions:
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|
*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* License 2: Modified BSD
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*
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* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
|
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
|
|
* Inc. unless otherwise expressly agreed to in writing between Synopsys
|
|
* and you.
|
|
*
|
|
* The Software IS NOT an item of Licensed Software or Licensed Product
|
|
* under any End User Software License Agreement or Agreement for Licensed
|
|
* Product with Synopsys or any supplement thereto. Permission is hereby
|
|
* granted, free of charge, to any person obtaining a copy of this software
|
|
* annotated with this license and the Software, to deal in the Software
|
|
* without restriction, including without limitation the rights to use,
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|
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
|
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* of the Software, and to permit persons to whom the Software is furnished
|
|
* to do so, subject to the following conditions:
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*
|
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* The above copyright notice and this permission notice shall be included
|
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* in all copies or substantial portions of the Software.
|
|
*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
|
|
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
|
* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __XGBE_H__
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#define __XGBE_H__
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#include "xgbe_osdep.h"
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/* From linux/dcbnl.h */
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#define IEEE_8021QAZ_MAX_TCS 8
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#define XGBE_DRV_NAME "amd-xgbe"
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#define XGBE_DRV_VERSION "1.0.2"
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#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
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/* Descriptor related defines */
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#define XGBE_TX_DESC_CNT 512
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#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
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#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
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#define XGBE_RX_DESC_CNT 512
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#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
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/* Descriptors required for maximum contiguous TSO/GSO packet */
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#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
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/* Maximum possible descriptors needed for an SKB:
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* - Maximum number of SKB frags
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* - Maximum descriptors for contiguous TSO/GSO packet
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* - Possible context descriptor
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* - Possible TSO header descriptor
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*/
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#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
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#define XGBE_RX_MIN_BUF_SIZE 1522
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#define XGBE_RX_BUF_ALIGN 64
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#define XGBE_SKB_ALLOC_SIZE 256
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#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
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#define XGBE_MAX_DMA_CHANNELS 16
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#define XGBE_MAX_QUEUES 16
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#define XGBE_DMA_STOP_TIMEOUT 5
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/* DMA cache settings - Outer sharable, write-back, write-allocate */
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#define XGBE_DMA_OS_AXDOMAIN 0x2
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#define XGBE_DMA_OS_ARCACHE 0xb
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#define XGBE_DMA_OS_AWCACHE 0xf
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/* DMA cache settings - System, no caches used */
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#define XGBE_DMA_SYS_AXDOMAIN 0x3
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#define XGBE_DMA_SYS_ARCACHE 0x0
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#define XGBE_DMA_SYS_AWCACHE 0x0
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#define XGBE_DMA_INTERRUPT_MASK 0x31c7
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#define XGMAC_MIN_PACKET 60
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#define XGMAC_STD_PACKET_MTU 1500
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#define XGMAC_MAX_STD_PACKET 1518
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#define XGMAC_JUMBO_PACKET_MTU 9000
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#define XGMAC_MAX_JUMBO_PACKET 9018
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/* Common property names */
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#define XGBE_MAC_ADDR_PROPERTY "mac-address"
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#define XGBE_PHY_MODE_PROPERTY "phy-mode"
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#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
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#define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
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#define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
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#define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
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#define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
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#define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
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#define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
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#define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
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/* Device-tree clock names */
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#define XGBE_DMA_CLOCK "dma_clk"
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#define XGBE_PTP_CLOCK "ptp_clk"
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/* ACPI property names */
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#define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
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#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
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/* Timestamp support - values based on 50MHz PTP clock
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* 50MHz => 20 nsec
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*/
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#define XGBE_TSTAMP_SSINC 20
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#define XGBE_TSTAMP_SNSINC 0
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/* Driver PMT macros */
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#define XGMAC_DRIVER_CONTEXT 1
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#define XGMAC_IOCTL_CONTEXT 2
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#define XGBE_FIFO_MAX 81920
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#define XGBE_TC_MIN_QUANTUM 10
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/* Helper macro for descriptor handling
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* Always use XGBE_GET_DESC_DATA to access the descriptor data
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* since the index is free-running and needs to be and-ed
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* with the descriptor count value of the ring to index to
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* the proper descriptor data.
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*/
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#define XGBE_GET_DESC_DATA(_ring, _idx) \
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((_ring)->rdata + \
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((_idx) & ((_ring)->rdesc_count - 1)))
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/* Default coalescing parameters */
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#define XGMAC_INIT_DMA_TX_USECS 1000
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#define XGMAC_INIT_DMA_TX_FRAMES 25
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#define XGMAC_MAX_DMA_RIWT 0xff
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#define XGMAC_INIT_DMA_RX_USECS 30
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#define XGMAC_INIT_DMA_RX_FRAMES 25
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/* Flow control queue count */
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#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
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/* Maximum MAC address hash table size (256 bits = 8 bytes) */
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#define XGBE_MAC_HASH_TABLE_SIZE 8
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/* Receive Side Scaling */
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#define XGBE_RSS_HASH_KEY_SIZE 40
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#define XGBE_RSS_MAX_TABLE_SIZE 256
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#define XGBE_RSS_LOOKUP_TABLE_TYPE 0
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#define XGBE_RSS_HASH_KEY_TYPE 1
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/* Auto-negotiation */
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#define XGBE_AN_MS_TIMEOUT 500
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#define XGBE_LINK_TIMEOUT 10
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#define XGBE_AN_INT_CMPLT 0x01
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#define XGBE_AN_INC_LINK 0x02
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#define XGBE_AN_PG_RCV 0x04
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#define XGBE_AN_INT_MASK 0x07
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/* Rate-change complete wait/retry count */
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#define XGBE_RATECHANGE_COUNT 500
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/* Default SerDes settings */
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#define XGBE_SPEED_10000_BLWC 0
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#define XGBE_SPEED_10000_CDR 0x7
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#define XGBE_SPEED_10000_PLL 0x1
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#define XGBE_SPEED_10000_PQ 0x12
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#define XGBE_SPEED_10000_RATE 0x0
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#define XGBE_SPEED_10000_TXAMP 0xa
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#define XGBE_SPEED_10000_WORD 0x7
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#define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
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#define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
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#define XGBE_SPEED_2500_BLWC 1
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#define XGBE_SPEED_2500_CDR 0x2
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#define XGBE_SPEED_2500_PLL 0x0
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#define XGBE_SPEED_2500_PQ 0xa
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#define XGBE_SPEED_2500_RATE 0x1
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#define XGBE_SPEED_2500_TXAMP 0xf
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#define XGBE_SPEED_2500_WORD 0x1
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#define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3
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#define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0
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#define XGBE_SPEED_1000_BLWC 1
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#define XGBE_SPEED_1000_CDR 0x2
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#define XGBE_SPEED_1000_PLL 0x0
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#define XGBE_SPEED_1000_PQ 0xa
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#define XGBE_SPEED_1000_RATE 0x3
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#define XGBE_SPEED_1000_TXAMP 0xf
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#define XGBE_SPEED_1000_WORD 0x1
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#define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3
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#define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0
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struct xgbe_prv_data;
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struct xgbe_packet_data {
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struct mbuf *m;
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unsigned int attributes;
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unsigned int errors;
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unsigned int rdesc_count;
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unsigned int length;
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u64 rx_tstamp;
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unsigned int tx_packets;
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unsigned int tx_bytes;
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};
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/* Common Rx and Tx descriptor mapping */
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struct xgbe_ring_desc {
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__le32 desc0;
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__le32 desc1;
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__le32 desc2;
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__le32 desc3;
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};
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/* Tx-related ring data */
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struct xgbe_tx_ring_data {
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unsigned int packets; /* BQL packet count */
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unsigned int bytes; /* BQL byte count */
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};
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/* Rx-related ring data */
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struct xgbe_rx_ring_data {
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unsigned short hdr_len; /* Length of received header */
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unsigned short len; /* Length of received packet */
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};
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/* Structure used to hold information related to the descriptor
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* and the packet associated with the descriptor (always use
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* use the XGBE_GET_DESC_DATA macro to access this data from the ring)
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*/
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struct xgbe_ring_data {
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struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
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bus_addr_t rdata_paddr;
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bus_dma_tag_t mbuf_dmat;
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bus_dmamap_t mbuf_map;
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bus_addr_t mbuf_hdr_paddr;
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bus_addr_t mbuf_data_paddr;
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bus_size_t mbuf_len;
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int mbuf_free;
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struct mbuf *mb;
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struct xgbe_tx_ring_data tx; /* Tx-related data */
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struct xgbe_rx_ring_data rx; /* Rx-related data */
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};
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struct xgbe_ring {
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/* Ring lock - used just for TX rings at the moment */
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spinlock_t lock;
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/* Per packet related information */
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struct xgbe_packet_data packet_data;
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/* Virtual/DMA addresses and count of allocated descriptor memory */
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struct xgbe_ring_desc *rdesc;
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bus_dmamap_t rdesc_map;
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bus_dma_tag_t rdesc_dmat;
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bus_addr_t rdesc_paddr;
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unsigned int rdesc_count;
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bus_dma_tag_t mbuf_dmat;
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bus_dmamap_t mbuf_map;
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/* Array of descriptor data corresponding the descriptor memory
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* (always use the XGBE_GET_DESC_DATA macro to access this data)
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*/
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struct xgbe_ring_data *rdata;
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/* Ring index values
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* cur - Tx: index of descriptor to be used for current transfer
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* Rx: index of descriptor to check for packet availability
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* dirty - Tx: index of descriptor to check for transfer complete
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* Rx: index of descriptor to check for buffer reallocation
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*/
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unsigned int cur;
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unsigned int dirty;
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|
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/* Coalesce frame count used for interrupt bit setting */
|
|
unsigned int coalesce_count;
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union {
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struct {
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unsigned int queue_stopped;
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unsigned int xmit_more;
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unsigned short cur_mss;
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unsigned short cur_vlan_ctag;
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} tx;
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};
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} __aligned(CACHE_LINE_SIZE);
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|
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/* Structure used to describe the descriptor rings associated with
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* a DMA channel.
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*/
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struct xgbe_channel {
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char name[16];
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|
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/* Address of private data area for device */
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struct xgbe_prv_data *pdata;
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|
|
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/* Queue index and base address of queue's DMA registers */
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|
unsigned int queue_index;
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bus_space_tag_t dma_tag;
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bus_space_handle_t dma_handle;
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|
|
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/* Per channel interrupt irq number */
|
|
struct resource *dma_irq_res;
|
|
void *dma_irq_tag;
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|
|
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unsigned int saved_ier;
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|
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struct xgbe_ring *tx_ring;
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struct xgbe_ring *rx_ring;
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} __aligned(CACHE_LINE_SIZE);
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|
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enum xgbe_state {
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XGBE_DOWN,
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XGBE_LINK_INIT,
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XGBE_LINK_ERR,
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};
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|
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enum xgbe_int {
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XGMAC_INT_DMA_CH_SR_TI,
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XGMAC_INT_DMA_CH_SR_TPS,
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XGMAC_INT_DMA_CH_SR_TBU,
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XGMAC_INT_DMA_CH_SR_RI,
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XGMAC_INT_DMA_CH_SR_RBU,
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XGMAC_INT_DMA_CH_SR_RPS,
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XGMAC_INT_DMA_CH_SR_TI_RI,
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XGMAC_INT_DMA_CH_SR_FBE,
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XGMAC_INT_DMA_ALL,
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};
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enum xgbe_int_state {
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XGMAC_INT_STATE_SAVE,
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XGMAC_INT_STATE_RESTORE,
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};
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enum xgbe_speed {
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XGBE_SPEED_1000 = 0,
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XGBE_SPEED_2500,
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XGBE_SPEED_10000,
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XGBE_SPEEDS,
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};
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|
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enum xgbe_an {
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XGBE_AN_READY = 0,
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XGBE_AN_PAGE_RECEIVED,
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XGBE_AN_INCOMPAT_LINK,
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XGBE_AN_COMPLETE,
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XGBE_AN_NO_LINK,
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XGBE_AN_ERROR,
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|
};
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|
|
|
enum xgbe_rx {
|
|
XGBE_RX_BPA = 0,
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XGBE_RX_XNP,
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XGBE_RX_COMPLETE,
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|
XGBE_RX_ERROR,
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};
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|
|
|
enum xgbe_mode {
|
|
XGBE_MODE_KR = 0,
|
|
XGBE_MODE_KX,
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|
};
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|
|
|
enum xgbe_speedset {
|
|
XGBE_SPEEDSET_1000_10000 = 0,
|
|
XGBE_SPEEDSET_2500_10000,
|
|
};
|
|
|
|
struct xgbe_phy {
|
|
u32 supported;
|
|
u32 advertising;
|
|
u32 lp_advertising;
|
|
|
|
int address;
|
|
|
|
int autoneg;
|
|
int speed;
|
|
int duplex;
|
|
|
|
int link;
|
|
|
|
int pause_autoneg;
|
|
int tx_pause;
|
|
int rx_pause;
|
|
};
|
|
|
|
struct xgbe_mmc_stats {
|
|
/* Tx Stats */
|
|
u64 txoctetcount_gb;
|
|
u64 txframecount_gb;
|
|
u64 txbroadcastframes_g;
|
|
u64 txmulticastframes_g;
|
|
u64 tx64octets_gb;
|
|
u64 tx65to127octets_gb;
|
|
u64 tx128to255octets_gb;
|
|
u64 tx256to511octets_gb;
|
|
u64 tx512to1023octets_gb;
|
|
u64 tx1024tomaxoctets_gb;
|
|
u64 txunicastframes_gb;
|
|
u64 txmulticastframes_gb;
|
|
u64 txbroadcastframes_gb;
|
|
u64 txunderflowerror;
|
|
u64 txoctetcount_g;
|
|
u64 txframecount_g;
|
|
u64 txpauseframes;
|
|
u64 txvlanframes_g;
|
|
|
|
/* Rx Stats */
|
|
u64 rxframecount_gb;
|
|
u64 rxoctetcount_gb;
|
|
u64 rxoctetcount_g;
|
|
u64 rxbroadcastframes_g;
|
|
u64 rxmulticastframes_g;
|
|
u64 rxcrcerror;
|
|
u64 rxrunterror;
|
|
u64 rxjabbererror;
|
|
u64 rxundersize_g;
|
|
u64 rxoversize_g;
|
|
u64 rx64octets_gb;
|
|
u64 rx65to127octets_gb;
|
|
u64 rx128to255octets_gb;
|
|
u64 rx256to511octets_gb;
|
|
u64 rx512to1023octets_gb;
|
|
u64 rx1024tomaxoctets_gb;
|
|
u64 rxunicastframes_g;
|
|
u64 rxlengtherror;
|
|
u64 rxoutofrangetype;
|
|
u64 rxpauseframes;
|
|
u64 rxfifooverflow;
|
|
u64 rxvlanframes_gb;
|
|
u64 rxwatchdogerror;
|
|
};
|
|
|
|
struct xgbe_ext_stats {
|
|
u64 tx_tso_packets;
|
|
u64 rx_split_header_packets;
|
|
u64 rx_buffer_unavailable;
|
|
};
|
|
|
|
struct xgbe_hw_if {
|
|
int (*tx_complete)(struct xgbe_ring_desc *);
|
|
|
|
int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
|
|
int (*config_rx_mode)(struct xgbe_prv_data *);
|
|
|
|
int (*enable_rx_csum)(struct xgbe_prv_data *);
|
|
int (*disable_rx_csum)(struct xgbe_prv_data *);
|
|
|
|
int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
|
|
int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
|
|
int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
|
|
int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
|
|
int (*update_vlan_hash_table)(struct xgbe_prv_data *);
|
|
|
|
int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
|
|
void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
|
|
int (*set_gmii_speed)(struct xgbe_prv_data *);
|
|
int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
|
|
int (*set_xgmii_speed)(struct xgbe_prv_data *);
|
|
|
|
void (*enable_tx)(struct xgbe_prv_data *);
|
|
void (*disable_tx)(struct xgbe_prv_data *);
|
|
void (*enable_rx)(struct xgbe_prv_data *);
|
|
void (*disable_rx)(struct xgbe_prv_data *);
|
|
|
|
void (*powerup_tx)(struct xgbe_prv_data *);
|
|
void (*powerdown_tx)(struct xgbe_prv_data *);
|
|
void (*powerup_rx)(struct xgbe_prv_data *);
|
|
void (*powerdown_rx)(struct xgbe_prv_data *);
|
|
|
|
int (*init)(struct xgbe_prv_data *);
|
|
int (*exit)(struct xgbe_prv_data *);
|
|
|
|
int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
|
|
int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
|
|
void (*dev_xmit)(struct xgbe_channel *);
|
|
int (*dev_read)(struct xgbe_channel *);
|
|
void (*tx_desc_init)(struct xgbe_channel *);
|
|
void (*rx_desc_init)(struct xgbe_channel *);
|
|
void (*tx_desc_reset)(struct xgbe_ring_data *);
|
|
void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
|
|
unsigned int);
|
|
int (*is_last_desc)(struct xgbe_ring_desc *);
|
|
int (*is_context_desc)(struct xgbe_ring_desc *);
|
|
void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
|
|
|
|
/* For FLOW ctrl */
|
|
int (*config_tx_flow_control)(struct xgbe_prv_data *);
|
|
int (*config_rx_flow_control)(struct xgbe_prv_data *);
|
|
|
|
/* For RX coalescing */
|
|
int (*config_rx_coalesce)(struct xgbe_prv_data *);
|
|
int (*config_tx_coalesce)(struct xgbe_prv_data *);
|
|
unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
|
|
unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
|
|
|
|
/* For RX and TX threshold config */
|
|
int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
|
|
int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
|
|
|
|
/* For RX and TX Store and Forward Mode config */
|
|
int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
|
|
int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
|
|
|
|
/* For TX DMA Operate on Second Frame config */
|
|
int (*config_osp_mode)(struct xgbe_prv_data *);
|
|
|
|
/* For RX and TX PBL config */
|
|
int (*config_rx_pbl_val)(struct xgbe_prv_data *);
|
|
int (*get_rx_pbl_val)(struct xgbe_prv_data *);
|
|
int (*config_tx_pbl_val)(struct xgbe_prv_data *);
|
|
int (*get_tx_pbl_val)(struct xgbe_prv_data *);
|
|
int (*config_pblx8)(struct xgbe_prv_data *);
|
|
|
|
/* For MMC statistics */
|
|
void (*rx_mmc_int)(struct xgbe_prv_data *);
|
|
void (*tx_mmc_int)(struct xgbe_prv_data *);
|
|
void (*read_mmc_stats)(struct xgbe_prv_data *);
|
|
|
|
/* For Receive Side Scaling */
|
|
int (*disable_rss)(struct xgbe_prv_data *);
|
|
};
|
|
|
|
struct xgbe_phy_if {
|
|
/* For initial PHY setup */
|
|
void (*phy_init)(struct xgbe_prv_data *);
|
|
|
|
/* For PHY support when setting device up/down */
|
|
int (*phy_reset)(struct xgbe_prv_data *);
|
|
int (*phy_start)(struct xgbe_prv_data *);
|
|
void (*phy_stop)(struct xgbe_prv_data *);
|
|
|
|
/* For PHY support while device is up */
|
|
void (*phy_status)(struct xgbe_prv_data *);
|
|
int (*phy_config_aneg)(struct xgbe_prv_data *);
|
|
};
|
|
|
|
struct xgbe_desc_if {
|
|
int (*alloc_ring_resources)(struct xgbe_prv_data *);
|
|
void (*free_ring_resources)(struct xgbe_prv_data *);
|
|
int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *);
|
|
int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
|
|
struct xgbe_ring_data *);
|
|
void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
|
|
void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
|
|
void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
|
|
};
|
|
|
|
/* This structure contains flags that indicate what hardware features
|
|
* or configurations are present in the device.
|
|
*/
|
|
struct xgbe_hw_features {
|
|
/* HW Version */
|
|
unsigned int version;
|
|
|
|
/* HW Feature Register0 */
|
|
unsigned int gmii; /* 1000 Mbps support */
|
|
unsigned int vlhash; /* VLAN Hash Filter */
|
|
unsigned int sma; /* SMA(MDIO) Interface */
|
|
unsigned int rwk; /* PMT remote wake-up packet */
|
|
unsigned int mgk; /* PMT magic packet */
|
|
unsigned int mmc; /* RMON module */
|
|
unsigned int aoe; /* ARP Offload */
|
|
unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
|
|
unsigned int eee; /* Energy Efficient Ethernet */
|
|
unsigned int tx_coe; /* Tx Checksum Offload */
|
|
unsigned int rx_coe; /* Rx Checksum Offload */
|
|
unsigned int addn_mac; /* Additional MAC Addresses */
|
|
unsigned int ts_src; /* Timestamp Source */
|
|
unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
|
|
|
|
/* HW Feature Register1 */
|
|
unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
|
|
unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
|
|
unsigned int adv_ts_hi; /* Advance Timestamping High Word */
|
|
unsigned int dma_width; /* DMA width */
|
|
unsigned int dcb; /* DCB Feature */
|
|
unsigned int sph; /* Split Header Feature */
|
|
unsigned int tso; /* TCP Segmentation Offload */
|
|
unsigned int dma_debug; /* DMA Debug Registers */
|
|
unsigned int rss; /* Receive Side Scaling */
|
|
unsigned int tc_cnt; /* Number of Traffic Classes */
|
|
unsigned int hash_table_size; /* Hash Table Size */
|
|
unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
|
|
|
|
/* HW Feature Register2 */
|
|
unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
|
|
unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
|
|
unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
|
|
unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
|
|
unsigned int pps_out_num; /* Number of PPS outputs */
|
|
unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
|
|
};
|
|
|
|
struct xgbe_prv_data {
|
|
struct ifnet *netdev;
|
|
struct platform_device *pdev;
|
|
struct acpi_device *adev;
|
|
device_t dev;
|
|
|
|
/* ACPI or DT flag */
|
|
unsigned int use_acpi;
|
|
|
|
/* XGMAC/XPCS related mmio registers */
|
|
struct resource *xgmac_res; /* XGMAC CSRs */
|
|
struct resource *xpcs_res; /* XPCS MMD registers */
|
|
struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */
|
|
struct resource *sir0_res; /* SerDes integration registers (1/2) */
|
|
struct resource *sir1_res; /* SerDes integration registers (2/2) */
|
|
|
|
/* DMA tag */
|
|
bus_dma_tag_t dmat;
|
|
|
|
/* XPCS indirect addressing lock */
|
|
spinlock_t xpcs_lock;
|
|
|
|
/* Flags representing xgbe_state */
|
|
unsigned long dev_state;
|
|
|
|
struct resource *dev_irq_res;
|
|
struct resource *chan_irq_res[4];
|
|
void *dev_irq_tag;
|
|
unsigned int per_channel_irq;
|
|
|
|
struct xgbe_hw_if hw_if;
|
|
struct xgbe_phy_if phy_if;
|
|
struct xgbe_desc_if desc_if;
|
|
|
|
/* AXI DMA settings */
|
|
unsigned int coherent;
|
|
unsigned int axdomain;
|
|
unsigned int arcache;
|
|
unsigned int awcache;
|
|
|
|
/* Service routine support */
|
|
struct taskqueue *dev_workqueue;
|
|
struct task service_work;
|
|
struct callout service_timer;
|
|
|
|
/* Rings for Tx/Rx on a DMA channel */
|
|
struct xgbe_channel *channel;
|
|
unsigned int channel_count;
|
|
unsigned int tx_ring_count;
|
|
unsigned int tx_desc_count;
|
|
unsigned int rx_ring_count;
|
|
unsigned int rx_desc_count;
|
|
|
|
unsigned int tx_q_count;
|
|
unsigned int rx_q_count;
|
|
|
|
/* Tx/Rx common settings */
|
|
unsigned int pblx8;
|
|
|
|
/* Tx settings */
|
|
unsigned int tx_sf_mode;
|
|
unsigned int tx_threshold;
|
|
unsigned int tx_pbl;
|
|
unsigned int tx_osp_mode;
|
|
|
|
/* Rx settings */
|
|
unsigned int rx_sf_mode;
|
|
unsigned int rx_threshold;
|
|
unsigned int rx_pbl;
|
|
|
|
/* Tx coalescing settings */
|
|
unsigned int tx_usecs;
|
|
unsigned int tx_frames;
|
|
|
|
/* Rx coalescing settings */
|
|
unsigned int rx_riwt;
|
|
unsigned int rx_usecs;
|
|
unsigned int rx_frames;
|
|
|
|
/* Current Rx buffer size */
|
|
unsigned int rx_buf_size;
|
|
|
|
/* Flow control settings */
|
|
unsigned int pause_autoneg;
|
|
unsigned int tx_pause;
|
|
unsigned int rx_pause;
|
|
|
|
/* Receive Side Scaling settings */
|
|
u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
|
|
u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
|
|
u32 rss_options;
|
|
|
|
/* Netdev related settings */
|
|
unsigned char mac_addr[ETH_ALEN];
|
|
struct xgbe_mmc_stats mmc_stats;
|
|
struct xgbe_ext_stats ext_stats;
|
|
|
|
/* Device clocks */
|
|
struct clk *sysclk;
|
|
unsigned long sysclk_rate;
|
|
struct clk *ptpclk;
|
|
unsigned long ptpclk_rate;
|
|
|
|
/* DCB support */
|
|
unsigned int q2tc_map[XGBE_MAX_QUEUES];
|
|
unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
|
|
u8 num_tcs;
|
|
|
|
/* Hardware features of the device */
|
|
struct xgbe_hw_features hw_feat;
|
|
|
|
/* Device restart work structure */
|
|
struct task restart_work;
|
|
|
|
/* Keeps track of power mode */
|
|
unsigned int power_down;
|
|
|
|
/* Network interface message level setting */
|
|
u32 msg_enable;
|
|
|
|
/* Current PHY settings */
|
|
int phy_link;
|
|
int phy_speed;
|
|
|
|
/* MDIO/PHY related settings */
|
|
struct xgbe_phy phy;
|
|
int mdio_mmd;
|
|
unsigned long link_check;
|
|
|
|
char an_name[IFNAMSIZ + 32];
|
|
|
|
struct resource *an_irq_res;
|
|
void *an_irq_tag;
|
|
|
|
unsigned int speed_set;
|
|
|
|
/* SerDes UEFI configurable settings.
|
|
* Switching between modes/speeds requires new values for some
|
|
* SerDes settings. The values can be supplied as device
|
|
* properties in array format. The first array entry is for
|
|
* 1GbE, second for 2.5GbE and third for 10GbE
|
|
*/
|
|
u32 serdes_blwc[XGBE_SPEEDS];
|
|
u32 serdes_cdr_rate[XGBE_SPEEDS];
|
|
u32 serdes_pq_skew[XGBE_SPEEDS];
|
|
u32 serdes_tx_amp[XGBE_SPEEDS];
|
|
u32 serdes_dfe_tap_cfg[XGBE_SPEEDS];
|
|
u32 serdes_dfe_tap_ena[XGBE_SPEEDS];
|
|
|
|
/* Auto-negotiation state machine support */
|
|
unsigned int an_int;
|
|
struct sx an_mutex;
|
|
enum xgbe_an an_result;
|
|
enum xgbe_an an_state;
|
|
enum xgbe_rx kr_state;
|
|
enum xgbe_rx kx_state;
|
|
unsigned int an_supported;
|
|
unsigned int parallel_detect;
|
|
unsigned int fec_ability;
|
|
unsigned long an_start;
|
|
|
|
unsigned int lpm_ctrl; /* CTRL1 for resume */
|
|
};
|
|
|
|
/* Function prototypes*/
|
|
|
|
int xgbe_open(struct ifnet *);
|
|
int xgbe_close(struct ifnet *);
|
|
int xgbe_xmit(struct ifnet *, struct mbuf *);
|
|
int xgbe_change_mtu(struct ifnet *, int);
|
|
void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
|
|
void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
|
|
void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
|
|
void xgbe_get_all_hw_features(struct xgbe_prv_data *);
|
|
void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
|
|
void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
|
|
|
|
/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
|
|
#if 0
|
|
#define YDEBUG
|
|
#define YDEBUG_MDIO
|
|
#endif
|
|
|
|
/* For debug prints */
|
|
#ifdef YDEBUG
|
|
#define DBGPR(x...) printf(x)
|
|
#else
|
|
#define DBGPR(x...) do { } while (0)
|
|
#endif
|
|
|
|
#ifdef YDEBUG_MDIO
|
|
#define DBGPR_MDIO(x...) printf(x)
|
|
#else
|
|
#define DBGPR_MDIO(x...) do { } while (0)
|
|
#endif
|
|
|
|
#endif
|