6f675c9d20
In recent EFI the DTS entries changed for PCIe controller. This commit fixes internal PCIe, external is yet TBD. Submitted by: Dominik Ermel <der@semihalf.com> Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D4976
107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/*-
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* Copyright (c) 2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Common PCIe functions for Cavium Thunder SOC */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include "thunder_pcie_common.h"
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uint32_t
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range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size)
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{
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struct pcie_range *r;
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int tuple;
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for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
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r = &ranges[tuple];
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if (addr >= r->pci_base &&
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addr < (r->pci_base + r->size) &&
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size < r->size) {
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/* Address is within PCI range */
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return (1);
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}
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}
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/* Address is outside PCI range */
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return (0);
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}
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uint32_t
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range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size)
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{
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struct pcie_range *r;
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int tuple;
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for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
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r = &ranges[tuple];
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if (addr >= r->phys_base &&
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addr < (r->phys_base + r->size) &&
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size < r->size) {
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/* Address is within Physical range */
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return (1);
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}
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}
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/* Address is outside Physical range */
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return (0);
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}
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uint64_t
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range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr)
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{
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struct pcie_range *r;
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uint64_t offset;
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int tuple;
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/* Find physical address corresponding to given bus address */
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for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
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r = &ranges[tuple];
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if (pci_addr >= r->pci_base &&
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pci_addr < (r->pci_base + r->size)) {
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/* Given pci addr is in this range.
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* Translate bus addr to phys addr.
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*/
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offset = pci_addr - r->pci_base;
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return (r->phys_base + offset);
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}
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}
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return (0);
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}
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