658 lines
12 KiB
ArmAsm
658 lines
12 KiB
ArmAsm
/* $NetBSD: bcopyinout.S,v 1.11 2003/10/13 21:22:40 scw Exp $ */
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/*-
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Allen Briggs for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.s"
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#include <machine/asm.h>
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.L_arm_memcpy:
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.word _C_LABEL(_arm_memcpy)
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.L_min_memcpy_size:
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.word _C_LABEL(_min_memcpy_size)
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__FBSDID("$FreeBSD$");
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#ifdef _ARM_ARCH_5E
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#include <arm/arm/bcopyinout_xscale.S>
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#else
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.text
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.align 0
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#ifdef MULTIPROCESSOR
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.Lcpu_info:
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.word _C_LABEL(cpu_info)
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#else
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.Lcurpcb:
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.word _C_LABEL(__pcpu) + PC_CURPCB
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#endif
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#define SAVE_REGS stmfd sp!, {r4-r11}
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#define RESTORE_REGS ldmfd sp!, {r4-r11}
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#if defined(_ARM_ARCH_5E)
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#define HELLOCPP #
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#define PREFETCH(rx,o) pld [ rx , HELLOCPP (o) ]
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#else
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#define PREFETCH(rx,o)
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#endif
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/*
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* r0 = user space address
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* r1 = kernel space address
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* r2 = length
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*
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* Copies bytes from user space to kernel space
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*
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* We save/restore r4-r11:
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* r4-r11 are scratch
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*/
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ENTRY(copyin)
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/* Quick exit if length is zero */
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teq r2, #0
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moveq r0, #0
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RETeq
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ldr r3, .L_arm_memcpy
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ldr r3, [r3]
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cmp r3, #0
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beq .Lnormal
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ldr r3, .L_min_memcpy_size
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ldr r3, [r3]
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cmp r2, r3
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blt .Lnormal
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stmfd sp!, {r0-r2, r4, lr}
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mov r3, r0
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mov r0, r1
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mov r1, r3
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mov r3, #2 /* SRC_IS_USER */
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ldr r4, .L_arm_memcpy
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mov lr, pc
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ldr pc, [r4]
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cmp r0, #0
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ldmfd sp!, {r0-r2, r4, lr}
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moveq r0, #0
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RETeq
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.Lnormal:
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SAVE_REGS
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#ifdef MULTIPROCESSOR
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/* XXX Probably not appropriate for non-Hydra SMPs */
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stmfd sp!, {r0-r2, r14}
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bl _C_LABEL(cpu_number)
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ldr r4, .Lcpu_info
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ldr r4, [r4, r0, lsl #2]
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ldr r4, [r4, #CI_CURPCB]
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ldmfd sp!, {r0-r2, r14}
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#else
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ldr r4, .Lcurpcb
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ldr r4, [r4]
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#endif
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ldr r5, [r4, #PCB_ONFAULT]
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adr r3, .Lcopyfault
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str r3, [r4, #PCB_ONFAULT]
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PREFETCH(r0, 0)
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PREFETCH(r1, 0)
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/*
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* If not too many bytes, take the slow path.
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*/
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cmp r2, #0x08
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blt .Licleanup
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/*
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* Align destination to word boundary.
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*/
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and r6, r1, #0x3
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ldr pc, [pc, r6, lsl #2]
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b .Lialend
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.word .Lialend
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.word .Lial3
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.word .Lial2
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.word .Lial1
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.Lial3: ldrbt r6, [r0], #1
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sub r2, r2, #1
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strb r6, [r1], #1
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.Lial2: ldrbt r7, [r0], #1
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sub r2, r2, #1
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strb r7, [r1], #1
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.Lial1: ldrbt r6, [r0], #1
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sub r2, r2, #1
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strb r6, [r1], #1
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.Lialend:
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/*
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* If few bytes left, finish slow.
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*/
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cmp r2, #0x08
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blt .Licleanup
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/*
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* If source is not aligned, finish slow.
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*/
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ands r3, r0, #0x03
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bne .Licleanup
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cmp r2, #0x60 /* Must be > 0x5f for unrolled cacheline */
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blt .Licleanup8
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/*
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* Align destination to cacheline boundary.
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* If source and destination are nicely aligned, this can be a big
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* win. If not, it's still cheaper to copy in groups of 32 even if
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* we don't get the nice cacheline alignment.
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*/
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and r6, r1, #0x1f
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ldr pc, [pc, r6]
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b .Licaligned
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.word .Licaligned
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.word .Lical28
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.word .Lical24
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.word .Lical20
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.word .Lical16
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.word .Lical12
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.word .Lical8
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.word .Lical4
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.Lical28:ldrt r6, [r0], #4
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sub r2, r2, #4
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str r6, [r1], #4
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.Lical24:ldrt r7, [r0], #4
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sub r2, r2, #4
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str r7, [r1], #4
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.Lical20:ldrt r6, [r0], #4
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sub r2, r2, #4
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str r6, [r1], #4
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.Lical16:ldrt r7, [r0], #4
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sub r2, r2, #4
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str r7, [r1], #4
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.Lical12:ldrt r6, [r0], #4
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sub r2, r2, #4
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str r6, [r1], #4
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.Lical8:ldrt r7, [r0], #4
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sub r2, r2, #4
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str r7, [r1], #4
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.Lical4:ldrt r6, [r0], #4
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sub r2, r2, #4
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str r6, [r1], #4
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/*
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* We start with > 0x40 bytes to copy (>= 0x60 got us into this
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* part of the code, and we may have knocked that down by as much
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* as 0x1c getting aligned).
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*
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* This loop basically works out to:
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* do {
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* prefetch-next-cacheline(s)
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* bytes -= 0x20;
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* copy cacheline
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* } while (bytes >= 0x40);
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* bytes -= 0x20;
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* copy cacheline
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*/
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.Licaligned:
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PREFETCH(r0, 32)
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PREFETCH(r1, 32)
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sub r2, r2, #0x20
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/* Copy a cacheline */
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ldrt r10, [r0], #4
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ldrt r11, [r0], #4
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ldrt r6, [r0], #4
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ldrt r7, [r0], #4
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ldrt r8, [r0], #4
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ldrt r9, [r0], #4
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stmia r1!, {r10-r11}
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ldrt r10, [r0], #4
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ldrt r11, [r0], #4
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stmia r1!, {r6-r11}
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cmp r2, #0x40
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bge .Licaligned
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sub r2, r2, #0x20
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/* Copy a cacheline */
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ldrt r10, [r0], #4
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ldrt r11, [r0], #4
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ldrt r6, [r0], #4
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ldrt r7, [r0], #4
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ldrt r8, [r0], #4
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ldrt r9, [r0], #4
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stmia r1!, {r10-r11}
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ldrt r10, [r0], #4
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ldrt r11, [r0], #4
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stmia r1!, {r6-r11}
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cmp r2, #0x08
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blt .Liprecleanup
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.Licleanup8:
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ldrt r8, [r0], #4
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ldrt r9, [r0], #4
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sub r2, r2, #8
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stmia r1!, {r8, r9}
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cmp r2, #8
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bge .Licleanup8
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.Liprecleanup:
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/*
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* If we're done, bail.
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*/
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cmp r2, #0
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beq .Lout
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.Licleanup:
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and r6, r2, #0x3
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ldr pc, [pc, r6, lsl #2]
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b .Licend
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.word .Lic4
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.word .Lic1
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.word .Lic2
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.word .Lic3
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.Lic4: ldrbt r6, [r0], #1
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sub r2, r2, #1
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strb r6, [r1], #1
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.Lic3: ldrbt r7, [r0], #1
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sub r2, r2, #1
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strb r7, [r1], #1
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.Lic2: ldrbt r6, [r0], #1
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sub r2, r2, #1
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strb r6, [r1], #1
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.Lic1: ldrbt r7, [r0], #1
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subs r2, r2, #1
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strb r7, [r1], #1
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.Licend:
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bne .Licleanup
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.Liout:
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mov r0, #0
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str r5, [r4, #PCB_ONFAULT]
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RESTORE_REGS
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RET
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.Lcopyfault:
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mov r0, #14 /* EFAULT */
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str r5, [r4, #PCB_ONFAULT]
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RESTORE_REGS
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RET
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/*
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* r0 = kernel space address
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* r1 = user space address
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* r2 = length
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*
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* Copies bytes from kernel space to user space
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*
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* We save/restore r4-r11:
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* r4-r11 are scratch
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*/
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ENTRY(copyout)
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/* Quick exit if length is zero */
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teq r2, #0
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moveq r0, #0
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RETeq
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ldr r3, .L_arm_memcpy
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ldr r3, [r3]
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cmp r3, #0
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beq .Lnormale
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ldr r3, .L_min_memcpy_size
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ldr r3, [r3]
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cmp r2, r3
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blt .Lnormale
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stmfd sp!, {r0-r2, r4, lr}
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mov r3, r0
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mov r0, r1
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mov r1, r3
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mov r3, #1 /* DST_IS_USER */
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ldr r4, .L_arm_memcpy
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mov lr, pc
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ldr pc, [r4]
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cmp r0, #0
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ldmfd sp!, {r0-r2, r4, lr}
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moveq r0, #0
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RETeq
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.Lnormale:
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SAVE_REGS
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#ifdef MULTIPROCESSOR
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/* XXX Probably not appropriate for non-Hydra SMPs */
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stmfd sp!, {r0-r2, r14}
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bl _C_LABEL(cpu_number)
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ldr r4, .Lcpu_info
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ldr r4, [r4, r0, lsl #2]
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ldr r4, [r4, #CI_CURPCB]
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ldmfd sp!, {r0-r2, r14}
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#else
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ldr r4, .Lcurpcb
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ldr r4, [r4]
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#endif
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ldr r5, [r4, #PCB_ONFAULT]
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adr r3, .Lcopyfault
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str r3, [r4, #PCB_ONFAULT]
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PREFETCH(r0, 0)
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PREFETCH(r1, 0)
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/*
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* If not too many bytes, take the slow path.
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*/
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cmp r2, #0x08
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blt .Lcleanup
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/*
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* Align destination to word boundary.
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*/
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and r6, r1, #0x3
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ldr pc, [pc, r6, lsl #2]
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b .Lalend
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.word .Lalend
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.word .Lal3
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.word .Lal2
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.word .Lal1
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.Lal3: ldrb r6, [r0], #1
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sub r2, r2, #1
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strbt r6, [r1], #1
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.Lal2: ldrb r7, [r0], #1
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sub r2, r2, #1
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strbt r7, [r1], #1
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.Lal1: ldrb r6, [r0], #1
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sub r2, r2, #1
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strbt r6, [r1], #1
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.Lalend:
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/*
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* If few bytes left, finish slow.
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*/
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cmp r2, #0x08
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blt .Lcleanup
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/*
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* If source is not aligned, finish slow.
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*/
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ands r3, r0, #0x03
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bne .Lcleanup
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cmp r2, #0x60 /* Must be > 0x5f for unrolled cacheline */
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blt .Lcleanup8
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/*
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* Align source & destination to cacheline boundary.
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*/
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and r6, r1, #0x1f
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ldr pc, [pc, r6]
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b .Lcaligned
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.word .Lcaligned
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.word .Lcal28
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.word .Lcal24
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.word .Lcal20
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.word .Lcal16
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.word .Lcal12
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.word .Lcal8
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.word .Lcal4
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.Lcal28:ldr r6, [r0], #4
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sub r2, r2, #4
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strt r6, [r1], #4
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.Lcal24:ldr r7, [r0], #4
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sub r2, r2, #4
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strt r7, [r1], #4
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.Lcal20:ldr r6, [r0], #4
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sub r2, r2, #4
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strt r6, [r1], #4
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.Lcal16:ldr r7, [r0], #4
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sub r2, r2, #4
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strt r7, [r1], #4
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.Lcal12:ldr r6, [r0], #4
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sub r2, r2, #4
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strt r6, [r1], #4
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.Lcal8: ldr r7, [r0], #4
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sub r2, r2, #4
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strt r7, [r1], #4
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.Lcal4: ldr r6, [r0], #4
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sub r2, r2, #4
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strt r6, [r1], #4
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/*
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* We start with > 0x40 bytes to copy (>= 0x60 got us into this
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* part of the code, and we may have knocked that down by as much
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* as 0x1c getting aligned).
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*
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* This loop basically works out to:
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* do {
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* prefetch-next-cacheline(s)
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* bytes -= 0x20;
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* copy cacheline
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* } while (bytes >= 0x40);
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* bytes -= 0x20;
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* copy cacheline
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*/
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.Lcaligned:
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PREFETCH(r0, 32)
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PREFETCH(r1, 32)
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sub r2, r2, #0x20
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/* Copy a cacheline */
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ldmia r0!, {r6-r11}
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strt r6, [r1], #4
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strt r7, [r1], #4
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ldmia r0!, {r6-r7}
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strt r8, [r1], #4
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strt r9, [r1], #4
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strt r10, [r1], #4
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strt r11, [r1], #4
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strt r6, [r1], #4
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strt r7, [r1], #4
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cmp r2, #0x40
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bge .Lcaligned
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sub r2, r2, #0x20
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/* Copy a cacheline */
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ldmia r0!, {r6-r11}
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strt r6, [r1], #4
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strt r7, [r1], #4
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ldmia r0!, {r6-r7}
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strt r8, [r1], #4
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strt r9, [r1], #4
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strt r10, [r1], #4
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strt r11, [r1], #4
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strt r6, [r1], #4
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strt r7, [r1], #4
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cmp r2, #0x08
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blt .Lprecleanup
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.Lcleanup8:
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ldmia r0!, {r8-r9}
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sub r2, r2, #8
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strt r8, [r1], #4
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strt r9, [r1], #4
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cmp r2, #8
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bge .Lcleanup8
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.Lprecleanup:
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/*
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* If we're done, bail.
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*/
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cmp r2, #0
|
|
beq .Lout
|
|
|
|
.Lcleanup:
|
|
and r6, r2, #0x3
|
|
ldr pc, [pc, r6, lsl #2]
|
|
b .Lcend
|
|
.word .Lc4
|
|
.word .Lc1
|
|
.word .Lc2
|
|
.word .Lc3
|
|
.Lc4: ldrb r6, [r0], #1
|
|
sub r2, r2, #1
|
|
strbt r6, [r1], #1
|
|
.Lc3: ldrb r7, [r0], #1
|
|
sub r2, r2, #1
|
|
strbt r7, [r1], #1
|
|
.Lc2: ldrb r6, [r0], #1
|
|
sub r2, r2, #1
|
|
strbt r6, [r1], #1
|
|
.Lc1: ldrb r7, [r0], #1
|
|
subs r2, r2, #1
|
|
strbt r7, [r1], #1
|
|
.Lcend:
|
|
bne .Lcleanup
|
|
|
|
.Lout:
|
|
mov r0, #0
|
|
|
|
str r5, [r4, #PCB_ONFAULT]
|
|
RESTORE_REGS
|
|
|
|
RET
|
|
#endif
|
|
|
|
/*
|
|
* int badaddr_read_1(const uint8_t *src, uint8_t *dest)
|
|
*
|
|
* Copies a single 8-bit value from src to dest, returning 0 on success,
|
|
* else EFAULT if a page fault occurred.
|
|
*/
|
|
ENTRY(badaddr_read_1)
|
|
#ifdef MULTIPROCESSOR
|
|
/* XXX Probably not appropriate for non-Hydra SMPs */
|
|
stmfd sp!, {r0-r1, r14}
|
|
bl _C_LABEL(cpu_number)
|
|
ldr r2, .Lcpu_info
|
|
ldr r2, [r2, r0, lsl #2]
|
|
ldr r2, [r2, #CI_CURPCB]
|
|
ldmfd sp!, {r0-r1, r14}
|
|
#else
|
|
ldr r2, .Lcurpcb
|
|
ldr r2, [r2]
|
|
#endif
|
|
ldr ip, [r2, #PCB_ONFAULT]
|
|
adr r3, 1f
|
|
str r3, [r2, #PCB_ONFAULT]
|
|
nop
|
|
nop
|
|
nop
|
|
ldrb r3, [r0]
|
|
nop
|
|
nop
|
|
nop
|
|
strb r3, [r1]
|
|
mov r0, #0 /* No fault */
|
|
1: str ip, [r2, #PCB_ONFAULT]
|
|
RET
|
|
|
|
/*
|
|
* int badaddr_read_2(const uint16_t *src, uint16_t *dest)
|
|
*
|
|
* Copies a single 16-bit value from src to dest, returning 0 on success,
|
|
* else EFAULT if a page fault occurred.
|
|
*/
|
|
ENTRY(badaddr_read_2)
|
|
#ifdef MULTIPROCESSOR
|
|
/* XXX Probably not appropriate for non-Hydra SMPs */
|
|
stmfd sp!, {r0-r1, r14}
|
|
bl _C_LABEL(cpu_number)
|
|
ldr r2, .Lcpu_info
|
|
ldr r2, [r2, r0, lsl #2]
|
|
ldr r2, [r2, #CI_CURPCB]
|
|
ldmfd sp!, {r0-r1, r14}
|
|
#else
|
|
ldr r2, .Lcurpcb
|
|
ldr r2, [r2]
|
|
#endif
|
|
ldr ip, [r2, #PCB_ONFAULT]
|
|
adr r3, 1f
|
|
str r3, [r2, #PCB_ONFAULT]
|
|
nop
|
|
nop
|
|
nop
|
|
ldrh r3, [r0]
|
|
nop
|
|
nop
|
|
nop
|
|
strh r3, [r1]
|
|
mov r0, #0 /* No fault */
|
|
1: str ip, [r2, #PCB_ONFAULT]
|
|
RET
|
|
|
|
/*
|
|
* int badaddr_read_4(const uint32_t *src, uint32_t *dest)
|
|
*
|
|
* Copies a single 32-bit value from src to dest, returning 0 on success,
|
|
* else EFAULT if a page fault occurred.
|
|
*/
|
|
ENTRY(badaddr_read_4)
|
|
#ifdef MULTIPROCESSOR
|
|
/* XXX Probably not appropriate for non-Hydra SMPs */
|
|
stmfd sp!, {r0-r1, r14}
|
|
bl _C_LABEL(cpu_number)
|
|
ldr r2, .Lcpu_info
|
|
ldr r2, [r2, r0, lsl #2]
|
|
ldr r2, [r2, #CI_CURPCB]
|
|
ldmfd sp!, {r0-r1, r14}
|
|
#else
|
|
ldr r2, .Lcurpcb
|
|
ldr r2, [r2]
|
|
#endif
|
|
ldr ip, [r2, #PCB_ONFAULT]
|
|
adr r3, 1f
|
|
str r3, [r2, #PCB_ONFAULT]
|
|
nop
|
|
nop
|
|
nop
|
|
ldr r3, [r0]
|
|
nop
|
|
nop
|
|
nop
|
|
str r3, [r1]
|
|
mov r0, #0 /* No fault */
|
|
1: str ip, [r2, #PCB_ONFAULT]
|
|
RET
|
|
|