285 lines
7.4 KiB
ArmAsm
285 lines
7.4 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_arm8.S,v 1.2 2001/11/11 00:47:49 thorpej Exp $ */
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/*-
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* Copyright (c) 1997 ARM Limited
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ARM8 assembly functions for CPU / MMU / TLB specific operations
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*
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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ENTRY(arm8_clock_config)
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mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */
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bic r2, r3, #0x11 /* turn off dynamic clocking
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and clear L bit */
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mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
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bic r2, r3, r0 /* Clear bits */
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eor r2, r2, r1 /* XOR bits */
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bic r2, r2, #0x10 /* clear the L bit */
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bic r1, r2, #0x01 /* still keep dynamic clocking off */
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mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
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mov r0, r0 /* NOP */
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mov r0, r0 /* NOP */
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mov r0, r0 /* NOP */
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mov r0, r0 /* NOP */
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mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
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mov r0, r3 /* Return old value */
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RET
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/*
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* Functions to set the MMU Translation Table Base register
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*
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* We need to clean and flush the cache as it uses virtual
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* addresses that are about to change.
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*/
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ENTRY(arm8_setttb)
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit | F32_bit)
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msr cpsr_all, r1
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stmfd sp!, {r0-r3, lr}
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bl _C_LABEL(arm8_cache_cleanID)
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ldmfd sp!, {r0-r3, lr}
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0
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/* For good measure we will flush the IDC as well */
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mcr p15, 0, r0, c7, c7, 0
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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msr cpsr_all, r3
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RET
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/*
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* TLB functions
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*/
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ENTRY(arm8_tlb_flushID)
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mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
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RET
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ENTRY(arm8_tlb_flushID_SE)
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mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
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RET
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/*
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* Cache functions
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*/
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ENTRY(arm8_cache_flushID)
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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RET
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ENTRY(arm8_cache_flushID_E)
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mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
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RET
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ENTRY(arm8_cache_cleanID)
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mov r0, #0x00000000
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1: mov r2, r0
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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adds r0, r0, #0x04000000
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bne 1b
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RET
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ENTRY(arm8_cache_cleanID_E)
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mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */
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RET
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ENTRY(arm8_cache_purgeID)
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/*
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* ARM810 bug 3
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*
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* Clean and invalidate entry will not invalidate the entry
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* if the line was already clean. (mcr p15, 0, rd, c7, 15, 1)
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*
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* Instead of using the clean and invalidate entry operation
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* use a separate clean and invalidate entry operations.
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* i.e.
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* mcr p15, 0, rd, c7, c11, 1
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* mcr p15, 0, rd, c7, c7, 1
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*/
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mov r0, #0x00000000
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mrs r3, cpsr_all
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orr r2, r3, #(I32_bit | F32_bit)
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msr cpsr_all, r2
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1: mov r2, r0
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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add r2, r2, #0x10
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mcr p15, 0, r2, c7, c11, 1
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mcr p15, 0, r2, c7, c7, 1
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adds r0, r0, #0x04000000
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bne 1b
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msr cpsr_all, r3
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RET
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ENTRY(arm8_cache_purgeID_E)
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/*
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* ARM810 bug 3
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*
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* Clean and invalidate entry will not invalidate the entry
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* if the line was already clean. (mcr p15, 0, rd, c7, 15, 1)
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*
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* Instead of using the clean and invalidate entry operation
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* use a separate clean and invalidate entry operations.
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* i.e.
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* mcr p15, 0, rd, c7, c11, 1
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* mcr p15, 0, rd, c7, c7, 1
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*/
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mrs r3, cpsr_all
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orr r2, r3, #(I32_bit | F32_bit)
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msr cpsr_all, r2
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mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */
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mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
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msr cpsr_all, r3
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RET
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/*
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* Context switch.
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*
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* These is the CPU-specific parts of the context switcher cpu_switch()
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* These functions actually perform the TTB reload.
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*
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* NOTE: Special calling convention
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* r1, r4-r13 must be preserved
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*/
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ENTRY(arm8_context_switch)
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/* For good measure we will flush the IDC as well */
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
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#if 0
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/* For good measure we will flush the IDC as well */
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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#endif
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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RET
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