0f34084f95
mmc(4). For the most part, this consists of support for: - Switching the signal voltage (VCCQ) to 1.8 V or (if supported by the host controller) to 1.2 V, - setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2 register, - setting the power class in the eMMC device according to the core supply voltage (VCC), - using different bits for enabling a bus width of 4 and 8 bits in the the eMMC device at DDR or higher timings respectively, - arbitrating timings faster than high speed if there actually are additional devices on the same MMC bus. Given that support for DDR52 is not denoted by SDHCI capability registers, availability of that timing is indicated by a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI controllers so far. Generally, what it takes for a sdhci(4) front-end to enable support for DDR52 is to hook up the bridge method mmcbr_switch_vccq (which especially for 1.2 V signaling support is chip/board specific) and the sdhci_set_uhs_timing sdhci(4) method. As a side-effect, this change also fixes communication with some eMMC devices at SDR high speed mode with 52 MHz due to the signaling voltage and UHS bits in the SDHCI controller no longer being left in an inappropriate state. Compared to 52 MHz at SDR high speed which typically yields ~45 MB/s with the eMMC chips tested, throughput goes up to ~80 MB/s at DDR52. Additionally, this change already adds infrastructure and quite some code for modes up to HS400ES and SDR104 respectively (I did not want to add to much stuff at a time, though). Essentially, what is still missing in order to be able to activate support for these latter is is support for and handling of (re-)tuning. o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as hw.sdhci.quirk_set, which (when hooked up in the front-end) allow to set/clear sdhci(4) quirks for debugging and testing purposes. However, especially for SDHCI controllers on the PCI bus which have no specific support code so far and, thus, are picked up as generic SDHCI controllers, hw.sdhci.quirk_set allows for setting the necessary quirks (if required). o In mmc(4), check and handle the return values of some more function calls instead of assuming that everything went right. In case failures actually are not problematic, indicate that by casting the return value to void. Reviewed by: jmcneill
385 lines
9.9 KiB
C
385 lines
9.9 KiB
C
/*-
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* Copyright (c) 2017 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include <dev/mmc/bridge.h>
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#include <dev/sdhci/sdhci.h>
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#include "mmcbr_if.h"
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#include "sdhci_if.h"
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static const struct sdhci_acpi_device {
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const char* hid;
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int uid;
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const char *desc;
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u_int quirks;
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} sdhci_acpi_devices[] = {
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{ "80860F14", 1, "Intel Bay Trail eMMC 4.5 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ "80860F14", 3, "Intel Bay Trail SDXC Controller",
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ "80860F16", 0, "Intel Bay Trail SDXC Controller",
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ NULL, 0, NULL, 0}
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};
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static char *sdhci_ids[] = {
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"80860F14",
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"80860F16",
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NULL
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};
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struct sdhci_acpi_softc {
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u_int quirks; /* Chip specific quirks */
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struct resource *irq_res; /* IRQ resource */
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void *intrhand; /* Interrupt handle */
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struct sdhci_slot slot;
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struct resource *mem_res; /* Memory resource */
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};
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static void sdhci_acpi_intr(void *arg);
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static int sdhci_acpi_detach(device_t dev);
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static uint8_t
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sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_1(sc->mem_res, off);
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}
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static void
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sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint8_t val)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_1(sc->mem_res, off, val);
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}
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static uint16_t
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sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_2(sc->mem_res, off);
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}
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static void
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sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint16_t val)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_2(sc->mem_res, off, val);
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}
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static uint32_t
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sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_4(sc->mem_res, off);
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}
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static void
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sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t val)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_4(sc->mem_res, off, val);
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}
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static void
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sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_read_multi_stream_4(sc->mem_res, off, data, count);
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}
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static void
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sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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bus_write_multi_stream_4(sc->mem_res, off, data, count);
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}
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static const struct sdhci_acpi_device *
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sdhci_acpi_find_device(device_t dev)
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{
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const char *hid;
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int i, uid;
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ACPI_HANDLE handle;
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ACPI_STATUS status;
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hid = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids);
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if (hid == NULL)
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return (NULL);
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handle = acpi_get_handle(dev);
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status = acpi_GetInteger(handle, "_UID", &uid);
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if (ACPI_FAILURE(status))
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uid = 0;
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for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) {
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if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0)
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continue;
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if ((sdhci_acpi_devices[i].uid != 0) &&
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(sdhci_acpi_devices[i].uid != uid))
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continue;
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return (&sdhci_acpi_devices[i]);
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}
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return (NULL);
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}
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static int
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sdhci_acpi_probe(device_t dev)
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{
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const struct sdhci_acpi_device *acpi_dev;
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acpi_dev = sdhci_acpi_find_device(dev);
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if (acpi_dev == NULL)
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return (ENXIO);
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device_set_desc(dev, acpi_dev->desc);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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sdhci_acpi_attach(device_t dev)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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int rid, err;
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const struct sdhci_acpi_device *acpi_dev;
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acpi_dev = sdhci_acpi_find_device(dev);
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if (acpi_dev == NULL)
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return (ENXIO);
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sc->quirks = acpi_dev->quirks;
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/* Allocate IRQ. */
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "can't allocate IRQ\n");
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return (ENOMEM);
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}
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "can't allocate memory resource for slot\n");
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sdhci_acpi_detach(dev);
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return (ENOMEM);
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}
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sc->quirks &= ~sdhci_quirk_clear;
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sc->quirks |= sdhci_quirk_set;
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sc->slot.quirks = sc->quirks;
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err = sdhci_init_slot(dev, &sc->slot, 0);
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if (err) {
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device_printf(dev, "failed to init slot\n");
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sdhci_acpi_detach(dev);
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return (err);
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}
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/* Activate the interrupt */
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, sdhci_acpi_intr, sc, &sc->intrhand);
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if (err) {
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device_printf(dev, "can't setup IRQ\n");
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sdhci_acpi_detach(dev);
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return (err);
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}
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/* Process cards detection. */
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sdhci_start_slot(&sc->slot);
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return (0);
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}
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static int
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sdhci_acpi_detach(device_t dev)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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if (sc->intrhand)
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bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
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if (sc->irq_res)
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(sc->irq_res), sc->irq_res);
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if (sc->mem_res) {
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sdhci_cleanup_slot(&sc->slot);
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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}
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return (0);
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}
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static int
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sdhci_acpi_shutdown(device_t dev)
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{
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return (0);
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}
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static int
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sdhci_acpi_suspend(device_t dev)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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int err;
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err = bus_generic_suspend(dev);
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if (err)
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return (err);
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sdhci_generic_suspend(&sc->slot);
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return (0);
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}
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static int
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sdhci_acpi_resume(device_t dev)
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{
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struct sdhci_acpi_softc *sc = device_get_softc(dev);
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int err;
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sdhci_generic_resume(&sc->slot);
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err = bus_generic_resume(dev);
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if (err)
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return (err);
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return (0);
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}
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static void
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sdhci_acpi_intr(void *arg)
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{
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struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg;
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sdhci_generic_intr(&sc->slot);
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}
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static device_method_t sdhci_methods[] = {
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/* device_if */
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DEVMETHOD(device_probe, sdhci_acpi_probe),
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DEVMETHOD(device_attach, sdhci_acpi_attach),
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DEVMETHOD(device_detach, sdhci_acpi_detach),
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DEVMETHOD(device_shutdown, sdhci_acpi_shutdown),
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DEVMETHOD(device_suspend, sdhci_acpi_suspend),
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DEVMETHOD(device_resume, sdhci_acpi_resume),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
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DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
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/* mmcbr_if */
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DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
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DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
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DEVMETHOD(mmcbr_request, sdhci_generic_request),
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DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
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DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
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DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
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/* SDHCI accessors */
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DEVMETHOD(sdhci_read_1, sdhci_acpi_read_1),
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DEVMETHOD(sdhci_read_2, sdhci_acpi_read_2),
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DEVMETHOD(sdhci_read_4, sdhci_acpi_read_4),
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DEVMETHOD(sdhci_read_multi_4, sdhci_acpi_read_multi_4),
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DEVMETHOD(sdhci_write_1, sdhci_acpi_write_1),
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DEVMETHOD(sdhci_write_2, sdhci_acpi_write_2),
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DEVMETHOD(sdhci_write_4, sdhci_acpi_write_4),
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DEVMETHOD(sdhci_write_multi_4, sdhci_acpi_write_multi_4),
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DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
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DEVMETHOD_END
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};
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static driver_t sdhci_acpi_driver = {
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"sdhci_acpi",
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sdhci_methods,
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sizeof(struct sdhci_acpi_softc),
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};
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static devclass_t sdhci_acpi_devclass;
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DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, sdhci_acpi_devclass, NULL,
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NULL);
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MODULE_DEPEND(sdhci_acpi, sdhci, 1, 1, 1);
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MMC_DECLARE_BRIDGE(sdhci_acpi);
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