04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
657 lines
51 KiB
C
657 lines
51 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-l2t-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon l2t.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_L2T_TYPEDEFS_H__
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#define __CVMX_L2T_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
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static inline uint64_t CVMX_L2T_ERR_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
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cvmx_warn("CVMX_L2T_ERR not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180080000008ull);
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}
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#else
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#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
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#endif
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/**
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* cvmx_l2t_err
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*
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* L2T_ERR = L2 Tag Errors
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*
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* Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable
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*/
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union cvmx_l2t_err
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{
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uint64_t u64;
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struct cvmx_l2t_err_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_29_63 : 35;
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uint64_t fadru : 1; /**< Failing L2 Tag Upper Address Bit (Index[10])
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the FADRU contains the upper(MSB bit) cacheline index
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into the L2 Tag Store. */
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uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
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uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
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could not find an available/unlocked set (for
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replacement).
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Most likely, this is a result of SW mixing SET
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PARTITIONING with ADDRESS LOCKING. If SW allows
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another PP to LOCKDOWN all SETs available to PP#n,
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then a Rd/Wr Miss from PP#n will be unable
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to determine a 'valid' replacement set (since LOCKED
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addresses should NEVER be replaced).
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If such an event occurs, the HW will select the smallest
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available SET(specified by UMSK'x)' as the replacement
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set, and the address is unlocked. */
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uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
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uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
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the INDEX (which is ignored by HW - but reported to SW).
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The LDD(L1 load-miss) for the LOCK operation is completed
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successfully, however the address is NOT locked.
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NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
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into account. For example, if diagnostic PPx has
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UMSKx defined to only use SETs [1:0], and SET1 had
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been previously LOCKED, then an attempt to LOCK the
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last available SET0 would result in a LCKERR. (This
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is to ensure that at least 1 SET at each INDEX is
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not LOCKED for general use by other PPs). */
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uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
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(FSYN != 0), the FSET specifies the failing hit-set.
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NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
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is specified by the L2C_DBG[SET]. */
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uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index)
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the FADR contains the lower 10bit cacheline index
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into the L2 Tag Store. */
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uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the contents of this register contain the 6-bit
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syndrome for the hit set only.
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If (FSYN = 0), the SBE or DBE reported was for one of
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the "non-hit" sets at the failing index(FADR).
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NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
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is specified by the L2C_DBG[SET].
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If (FSYN != 0), the SBE or DBE reported was for the
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hit set at the failing index(FADR) and failing
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set(FSET).
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SW NOTE: To determine which "non-hit" set was in error,
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SW can use the L2C_DBG[L2T] debug feature to explicitly
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read the other sets at the failing index(FADR). When
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(FSYN !=0), then the FSET contains the failing hit-set.
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NOTE: A DED Error will always overwrite a SEC Error
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SYNDROME and FADR). */
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uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
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During every L2 Tag Probe, all 8 sets Tag's (at a
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given index) are checked for double bit errors(DBEs).
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This bit is set if ANY of the 8 sets contains a DBE.
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DBEs also generated an interrupt(if enabled). */
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uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
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During every L2 Tag Probe, all 8 sets Tag's (at a
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given index) are checked for single bit errors(SBEs).
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This bit is set if ANY of the 8 sets contains an SBE.
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SBEs are auto corrected in HW and generate an
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interrupt(if enabled). */
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uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
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Enable bit. When set, allows interrupts to be
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reported on double bit (uncorrectable) errors from
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the L2 Tag Arrays. */
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uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
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Enable bit. When set, allows interrupts to be
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reported on single bit (correctable) errors from
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the L2 Tag Arrays. */
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uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
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When set, enables 6-bit SEC/DED codeword for 19-bit
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L2 Tag Arrays [V,D,L,TAG[33:18]] */
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#else
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uint64_t ecc_ena : 1;
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uint64_t sec_intena : 1;
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uint64_t ded_intena : 1;
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uint64_t sec_err : 1;
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uint64_t ded_err : 1;
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uint64_t fsyn : 6;
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uint64_t fadr : 10;
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uint64_t fset : 3;
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uint64_t lckerr : 1;
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uint64_t lck_intena : 1;
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uint64_t lckerr2 : 1;
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uint64_t lck_intena2 : 1;
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uint64_t fadru : 1;
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uint64_t reserved_29_63 : 35;
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#endif
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} s;
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struct cvmx_l2t_err_cn30xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_28_63 : 36;
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uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
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uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
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could not find an available/unlocked set (for
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replacement).
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Most likely, this is a result of SW mixing SET
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PARTITIONING with ADDRESS LOCKING. If SW allows
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another PP to LOCKDOWN all SETs available to PP#n,
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then a Rd/Wr Miss from PP#n will be unable
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to determine a 'valid' replacement set (since LOCKED
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addresses should NEVER be replaced).
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If such an event occurs, the HW will select the smallest
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available SET(specified by UMSK'x)' as the replacement
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set, and the address is unlocked. */
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uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
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uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
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the INDEX (which is ignored by HW - but reported to SW).
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The LDD(L1 load-miss) for the LOCK operation is
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completed successfully, however the address is NOT
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locked.
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NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
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into account. For example, if diagnostic PPx has
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UMSKx defined to only use SETs [1:0], and SET1 had
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been previously LOCKED, then an attempt to LOCK the
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last available SET0 would result in a LCKERR. (This
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is to ensure that at least 1 SET at each INDEX is
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not LOCKED for general use by other PPs). */
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uint64_t reserved_23_23 : 1;
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uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4)
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
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(FSYN != 0), the FSET specifies the failing hit-set.
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NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
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is specified by the L2C_DBG[SET]. */
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uint64_t reserved_19_20 : 2;
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uint64_t fadr : 8; /**< Failing L2 Tag Store Index (8-bit)
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the FADR contains the 8bit cacheline index into the
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L2 Tag Store. */
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uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the contents of this register contain the 6-bit
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syndrome for the hit set only.
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If (FSYN = 0), the SBE or DBE reported was for one of
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the "non-hit" sets at the failing index(FADR).
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NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
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is specified by the L2C_DBG[SET].
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If (FSYN != 0), the SBE or DBE reported was for the
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hit set at the failing index(FADR) and failing
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set(FSET).
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SW NOTE: To determine which "non-hit" set was in error,
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SW can use the L2C_DBG[L2T] debug feature to explicitly
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read the other sets at the failing index(FADR). When
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(FSYN !=0), then the FSET contains the failing hit-set.
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NOTE: A DED Error will always overwrite a SEC Error
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SYNDROME and FADR). */
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uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
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During every L2 Tag Probe, all 8 sets Tag's (at a
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given index) are checked for double bit errors(DBEs).
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This bit is set if ANY of the 8 sets contains a DBE.
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DBEs also generated an interrupt(if enabled). */
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uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
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During every L2 Tag Probe, all 8 sets Tag's (at a
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given index) are checked for single bit errors(SBEs).
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This bit is set if ANY of the 8 sets contains an SBE.
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SBEs are auto corrected in HW and generate an
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interrupt(if enabled). */
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uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
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Enable bit. When set, allows interrupts to be
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reported on double bit (uncorrectable) errors from
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the L2 Tag Arrays. */
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uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
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Enable bit. When set, allows interrupts to be
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reported on single bit (correctable) errors from
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the L2 Tag Arrays. */
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uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
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When set, enables 6-bit SEC/DED codeword for 22-bit
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L2 Tag Arrays [V,D,L,TAG[33:15]] */
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#else
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uint64_t ecc_ena : 1;
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uint64_t sec_intena : 1;
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uint64_t ded_intena : 1;
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uint64_t sec_err : 1;
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uint64_t ded_err : 1;
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uint64_t fsyn : 6;
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uint64_t fadr : 8;
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uint64_t reserved_19_20 : 2;
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uint64_t fset : 2;
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uint64_t reserved_23_23 : 1;
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uint64_t lckerr : 1;
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uint64_t lck_intena : 1;
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uint64_t lckerr2 : 1;
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uint64_t lck_intena2 : 1;
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uint64_t reserved_28_63 : 36;
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#endif
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} cn30xx;
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struct cvmx_l2t_err_cn31xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_28_63 : 36;
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uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
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uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
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could not find an available/unlocked set (for
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replacement).
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Most likely, this is a result of SW mixing SET
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PARTITIONING with ADDRESS LOCKING. If SW allows
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another PP to LOCKDOWN all SETs available to PP#n,
|
|
then a Rd/Wr Miss from PP#n will be unable
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to determine a 'valid' replacement set (since LOCKED
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addresses should NEVER be replaced).
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If such an event occurs, the HW will select the smallest
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available SET(specified by UMSK'x)' as the replacement
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set, and the address is unlocked. */
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uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
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uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
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the INDEX (which is ignored by HW - but reported to SW).
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The LDD(L1 load-miss) for the LOCK operation is completed
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successfully, however the address is NOT locked.
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NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
|
|
into account. For example, if diagnostic PPx has
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|
UMSKx defined to only use SETs [1:0], and SET1 had
|
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been previously LOCKED, then an attempt to LOCK the
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last available SET0 would result in a LCKERR. (This
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is to ensure that at least 1 SET at each INDEX is
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not LOCKED for general use by other PPs). */
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uint64_t reserved_23_23 : 1;
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uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4)
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
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(FSYN != 0), the FSET specifies the failing hit-set.
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NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
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is specified by the L2C_DBG[SET]. */
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uint64_t reserved_20_20 : 1;
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uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index)
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When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the FADR contains the 9-bit cacheline index into the
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L2 Tag Store. */
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uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
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the contents of this register contain the 6-bit
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syndrome for the hit set only.
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If (FSYN = 0), the SBE or DBE reported was for one of
|
|
the "non-hit" sets at the failing index(FADR).
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
|
|
is specified by the L2C_DBG[SET].
|
|
If (FSYN != 0), the SBE or DBE reported was for the
|
|
hit set at the failing index(FADR) and failing
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|
set(FSET).
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|
SW NOTE: To determine which "non-hit" set was in error,
|
|
SW can use the L2C_DBG[L2T] debug feature to explicitly
|
|
read the other sets at the failing index(FADR). When
|
|
(FSYN !=0), then the FSET contains the failing hit-set.
|
|
NOTE: A DED Error will always overwrite a SEC Error
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|
SYNDROME and FADR). */
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|
uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
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|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for double bit errors(DBEs).
|
|
This bit is set if ANY of the 8 sets contains a DBE.
|
|
DBEs also generated an interrupt(if enabled). */
|
|
uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for single bit errors(SBEs).
|
|
This bit is set if ANY of the 8 sets contains an SBE.
|
|
SBEs are auto corrected in HW and generate an
|
|
interrupt(if enabled). */
|
|
uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
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|
Enable bit. When set, allows interrupts to be
|
|
reported on double bit (uncorrectable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
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|
Enable bit. When set, allows interrupts to be
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|
reported on single bit (correctable) errors from
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|
the L2 Tag Arrays. */
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|
uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
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When set, enables 6-bit SEC/DED codeword for 21-bit
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L2 Tag Arrays [V,D,L,TAG[33:16]] */
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#else
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uint64_t ecc_ena : 1;
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uint64_t sec_intena : 1;
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uint64_t ded_intena : 1;
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uint64_t sec_err : 1;
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uint64_t ded_err : 1;
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uint64_t fsyn : 6;
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uint64_t fadr : 9;
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uint64_t reserved_20_20 : 1;
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uint64_t fset : 2;
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uint64_t reserved_23_23 : 1;
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uint64_t lckerr : 1;
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uint64_t lck_intena : 1;
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uint64_t lckerr2 : 1;
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uint64_t lck_intena2 : 1;
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uint64_t reserved_28_63 : 36;
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#endif
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} cn31xx;
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struct cvmx_l2t_err_cn38xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_28_63 : 36;
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|
uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
|
|
uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
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|
could not find an available/unlocked set (for
|
|
replacement).
|
|
Most likely, this is a result of SW mixing SET
|
|
PARTITIONING with ADDRESS LOCKING. If SW allows
|
|
another PP to LOCKDOWN all SETs available to PP#n,
|
|
then a Rd/Wr Miss from PP#n will be unable
|
|
to determine a 'valid' replacement set (since LOCKED
|
|
addresses should NEVER be replaced).
|
|
If such an event occurs, the HW will select the smallest
|
|
available SET(specified by UMSK'x)' as the replacement
|
|
set, and the address is unlocked. */
|
|
uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
|
|
uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
|
|
the INDEX (which is ignored by HW - but reported to SW).
|
|
The LDD(L1 load-miss) for the LOCK operation is completed
|
|
successfully, however the address is NOT locked.
|
|
NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
|
|
into account. For example, if diagnostic PPx has
|
|
UMSKx defined to only use SETs [1:0], and SET1 had
|
|
been previously LOCKED, then an attempt to LOCK the
|
|
last available SET0 would result in a LCKERR. (This
|
|
is to ensure that at least 1 SET at each INDEX is
|
|
not LOCKED for general use by other PPs). */
|
|
uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
|
|
When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
|
|
(FSYN != 0), the FSET specifies the failing hit-set.
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
|
|
is specified by the L2C_DBG[SET]. */
|
|
uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index)
|
|
When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
|
|
the FADR contains the 10bit cacheline index into the
|
|
L2 Tag Store. */
|
|
uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
|
|
the contents of this register contain the 6-bit
|
|
syndrome for the hit set only.
|
|
If (FSYN = 0), the SBE or DBE reported was for one of
|
|
the "non-hit" sets at the failing index(FADR).
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
|
|
is specified by the L2C_DBG[SET].
|
|
If (FSYN != 0), the SBE or DBE reported was for the
|
|
hit set at the failing index(FADR) and failing
|
|
set(FSET).
|
|
SW NOTE: To determine which "non-hit" set was in error,
|
|
SW can use the L2C_DBG[L2T] debug feature to explicitly
|
|
read the other sets at the failing index(FADR). When
|
|
(FSYN !=0), then the FSET contains the failing hit-set.
|
|
NOTE: A DED Error will always overwrite a SEC Error
|
|
SYNDROME and FADR). */
|
|
uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for double bit errors(DBEs).
|
|
This bit is set if ANY of the 8 sets contains a DBE.
|
|
DBEs also generated an interrupt(if enabled). */
|
|
uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for single bit errors(SBEs).
|
|
This bit is set if ANY of the 8 sets contains an SBE.
|
|
SBEs are auto corrected in HW and generate an
|
|
interrupt(if enabled). */
|
|
uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
|
|
Enable bit. When set, allows interrupts to be
|
|
reported on double bit (uncorrectable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
|
|
Enable bit. When set, allows interrupts to be
|
|
reported on single bit (correctable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
|
|
When set, enables 6-bit SEC/DED codeword for 20-bit
|
|
L2 Tag Arrays [V,D,L,TAG[33:17]] */
|
|
#else
|
|
uint64_t ecc_ena : 1;
|
|
uint64_t sec_intena : 1;
|
|
uint64_t ded_intena : 1;
|
|
uint64_t sec_err : 1;
|
|
uint64_t ded_err : 1;
|
|
uint64_t fsyn : 6;
|
|
uint64_t fadr : 10;
|
|
uint64_t fset : 3;
|
|
uint64_t lckerr : 1;
|
|
uint64_t lck_intena : 1;
|
|
uint64_t lckerr2 : 1;
|
|
uint64_t lck_intena2 : 1;
|
|
uint64_t reserved_28_63 : 36;
|
|
#endif
|
|
} cn38xx;
|
|
struct cvmx_l2t_err_cn38xx cn38xxp2;
|
|
struct cvmx_l2t_err_cn50xx
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_28_63 : 36;
|
|
uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
|
|
uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
|
|
could not find an available/unlocked set (for
|
|
replacement).
|
|
Most likely, this is a result of SW mixing SET
|
|
PARTITIONING with ADDRESS LOCKING. If SW allows
|
|
another PP to LOCKDOWN all SETs available to PP#n,
|
|
then a Rd/Wr Miss from PP#n will be unable
|
|
to determine a 'valid' replacement set (since LOCKED
|
|
addresses should NEVER be replaced).
|
|
If such an event occurs, the HW will select the smallest
|
|
available SET(specified by UMSK'x)' as the replacement
|
|
set, and the address is unlocked. */
|
|
uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
|
|
uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
|
|
the INDEX (which is ignored by HW - but reported to SW).
|
|
The LDD(L1 load-miss) for the LOCK operation is completed
|
|
successfully, however the address is NOT locked.
|
|
NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
|
|
into account. For example, if diagnostic PPx has
|
|
UMSKx defined to only use SETs [1:0], and SET1 had
|
|
been previously LOCKED, then an attempt to LOCK the
|
|
last available SET0 would result in a LCKERR. (This
|
|
is to ensure that at least 1 SET at each INDEX is
|
|
not LOCKED for general use by other PPs). */
|
|
uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
|
|
When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
|
|
(FSYN != 0), the FSET specifies the failing hit-set.
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
|
|
is specified by the L2C_DBG[SET]. */
|
|
uint64_t reserved_18_20 : 3;
|
|
uint64_t fadr : 7; /**< Failing L2 Tag Address (7-bit Index)
|
|
When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
|
|
the FADR contains the lower 7bit cacheline index
|
|
into the L2 Tag Store. */
|
|
uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
|
|
the contents of this register contain the 6-bit
|
|
syndrome for the hit set only.
|
|
If (FSYN = 0), the SBE or DBE reported was for one of
|
|
the "non-hit" sets at the failing index(FADR).
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
|
|
is specified by the L2C_DBG[SET].
|
|
If (FSYN != 0), the SBE or DBE reported was for the
|
|
hit set at the failing index(FADR) and failing
|
|
set(FSET).
|
|
SW NOTE: To determine which "non-hit" set was in error,
|
|
SW can use the L2C_DBG[L2T] debug feature to explicitly
|
|
read the other sets at the failing index(FADR). When
|
|
(FSYN !=0), then the FSET contains the failing hit-set.
|
|
NOTE: A DED Error will always overwrite a SEC Error
|
|
SYNDROME and FADR). */
|
|
uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for double bit errors(DBEs).
|
|
This bit is set if ANY of the 8 sets contains a DBE.
|
|
DBEs also generated an interrupt(if enabled). */
|
|
uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for single bit errors(SBEs).
|
|
This bit is set if ANY of the 8 sets contains an SBE.
|
|
SBEs are auto corrected in HW and generate an
|
|
interrupt(if enabled). */
|
|
uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
|
|
Enable bit. When set, allows interrupts to be
|
|
reported on double bit (uncorrectable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
|
|
Enable bit. When set, allows interrupts to be
|
|
reported on single bit (correctable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
|
|
When set, enables 6-bit SEC/DED codeword for 23-bit
|
|
L2 Tag Arrays [V,D,L,TAG[33:14]] */
|
|
#else
|
|
uint64_t ecc_ena : 1;
|
|
uint64_t sec_intena : 1;
|
|
uint64_t ded_intena : 1;
|
|
uint64_t sec_err : 1;
|
|
uint64_t ded_err : 1;
|
|
uint64_t fsyn : 6;
|
|
uint64_t fadr : 7;
|
|
uint64_t reserved_18_20 : 3;
|
|
uint64_t fset : 3;
|
|
uint64_t lckerr : 1;
|
|
uint64_t lck_intena : 1;
|
|
uint64_t lckerr2 : 1;
|
|
uint64_t lck_intena2 : 1;
|
|
uint64_t reserved_28_63 : 36;
|
|
#endif
|
|
} cn50xx;
|
|
struct cvmx_l2t_err_cn52xx
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_28_63 : 36;
|
|
uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
|
|
uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
|
|
could not find an available/unlocked set (for
|
|
replacement).
|
|
Most likely, this is a result of SW mixing SET
|
|
PARTITIONING with ADDRESS LOCKING. If SW allows
|
|
another PP to LOCKDOWN all SETs available to PP#n,
|
|
then a Rd/Wr Miss from PP#n will be unable
|
|
to determine a 'valid' replacement set (since LOCKED
|
|
addresses should NEVER be replaced).
|
|
If such an event occurs, the HW will select the smallest
|
|
available SET(specified by UMSK'x)' as the replacement
|
|
set, and the address is unlocked. */
|
|
uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
|
|
uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
|
|
the INDEX (which is ignored by HW - but reported to SW).
|
|
The LDD(L1 load-miss) for the LOCK operation is completed
|
|
successfully, however the address is NOT locked.
|
|
NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
|
|
into account. For example, if diagnostic PPx has
|
|
UMSKx defined to only use SETs [1:0], and SET1 had
|
|
been previously LOCKED, then an attempt to LOCK the
|
|
last available SET0 would result in a LCKERR. (This
|
|
is to ensure that at least 1 SET at each INDEX is
|
|
not LOCKED for general use by other PPs). */
|
|
uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
|
|
When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
|
|
(FSYN != 0), the FSET specifies the failing hit-set.
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
|
|
is specified by the L2C_DBG[SET]. */
|
|
uint64_t reserved_20_20 : 1;
|
|
uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index)
|
|
When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
|
|
the FADR contains the lower 9bit cacheline index
|
|
into the L2 Tag Store. */
|
|
uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
|
|
the contents of this register contain the 6-bit
|
|
syndrome for the hit set only.
|
|
If (FSYN = 0), the SBE or DBE reported was for one of
|
|
the "non-hit" sets at the failing index(FADR).
|
|
NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
|
|
is specified by the L2C_DBG[SET].
|
|
If (FSYN != 0), the SBE or DBE reported was for the
|
|
hit set at the failing index(FADR) and failing
|
|
set(FSET).
|
|
SW NOTE: To determine which "non-hit" set was in error,
|
|
SW can use the L2C_DBG[L2T] debug feature to explicitly
|
|
read the other sets at the failing index(FADR). When
|
|
(FSYN !=0), then the FSET contains the failing hit-set.
|
|
NOTE: A DED Error will always overwrite a SEC Error
|
|
SYNDROME and FADR). */
|
|
uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for double bit errors(DBEs).
|
|
This bit is set if ANY of the 8 sets contains a DBE.
|
|
DBEs also generated an interrupt(if enabled). */
|
|
uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
|
|
During every L2 Tag Probe, all 8 sets Tag's (at a
|
|
given index) are checked for single bit errors(SBEs).
|
|
This bit is set if ANY of the 8 sets contains an SBE.
|
|
SBEs are auto corrected in HW and generate an
|
|
interrupt(if enabled). */
|
|
uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
|
|
Enable bit. When set, allows interrupts to be
|
|
reported on double bit (uncorrectable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
|
|
Enable bit. When set, allows interrupts to be
|
|
reported on single bit (correctable) errors from
|
|
the L2 Tag Arrays. */
|
|
uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
|
|
When set, enables 6-bit SEC/DED codeword for 21-bit
|
|
L2 Tag Arrays [V,D,L,TAG[33:16]] */
|
|
#else
|
|
uint64_t ecc_ena : 1;
|
|
uint64_t sec_intena : 1;
|
|
uint64_t ded_intena : 1;
|
|
uint64_t sec_err : 1;
|
|
uint64_t ded_err : 1;
|
|
uint64_t fsyn : 6;
|
|
uint64_t fadr : 9;
|
|
uint64_t reserved_20_20 : 1;
|
|
uint64_t fset : 3;
|
|
uint64_t lckerr : 1;
|
|
uint64_t lck_intena : 1;
|
|
uint64_t lckerr2 : 1;
|
|
uint64_t lck_intena2 : 1;
|
|
uint64_t reserved_28_63 : 36;
|
|
#endif
|
|
} cn52xx;
|
|
struct cvmx_l2t_err_cn52xx cn52xxp1;
|
|
struct cvmx_l2t_err_s cn56xx;
|
|
struct cvmx_l2t_err_s cn56xxp1;
|
|
struct cvmx_l2t_err_s cn58xx;
|
|
struct cvmx_l2t_err_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_l2t_err cvmx_l2t_err_t;
|
|
|
|
#endif
|