381a19cce0
previously know by StarSemi STR9104. Tested by the submitter on an Emprex NSD-100 board. Submitted by: Yohanes Nugroho <yohanes at gmail.com> Reviewed by: freebsd-arm, stas Obtained from: //depot/projects/str91xx/...
759 lines
17 KiB
C
759 lines
17 KiB
C
/*-
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* Copyright (c) 2009 Yohanes Nugroho <yohanes@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/types.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/vm_kern.h>
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#include <vm/pmap.h>
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#include <vm/vm_page.h>
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#include <vm/vm_extern.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include "econa_reg.h"
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#include "econa_var.h"
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static struct econa_softc *econa_softc;
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unsigned int CPU_clock = 200000000;
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unsigned int AHB_clock;
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unsigned int APB_clock;
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bs_protos(generic);
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bs_protos(generic_armv4);
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struct bus_space econa_bs_tag = {
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/* cookie */
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(void *) 0,
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/* mapping/unmapping */
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generic_bs_map,
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generic_bs_unmap,
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generic_bs_subregion,
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/* allocation/deallocation */
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generic_bs_alloc,
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generic_bs_free,
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/* barrier */
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generic_bs_barrier,
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/* read (single) */
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generic_bs_r_1,
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generic_armv4_bs_r_2,
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generic_bs_r_4,
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NULL,
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/* read multiple */
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generic_bs_rm_1,
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generic_armv4_bs_rm_2,
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generic_bs_rm_4,
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NULL,
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/* read region */
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generic_bs_rr_1,
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generic_armv4_bs_rr_2,
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generic_bs_rr_4,
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NULL,
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/* write (single) */
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generic_bs_w_1,
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generic_armv4_bs_w_2,
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generic_bs_w_4,
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NULL,
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/* write multiple */
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generic_bs_wm_1,
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generic_armv4_bs_wm_2,
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generic_bs_wm_4,
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NULL,
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/* write region */
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NULL,
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NULL,
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NULL,
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NULL,
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/* set multiple */
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NULL,
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NULL,
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NULL,
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NULL,
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/* set region */
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NULL,
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NULL,
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NULL,
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NULL,
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/* copy */
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NULL,
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NULL,
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NULL,
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NULL,
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/* read (single) stream */
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NULL,
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NULL,
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NULL,
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NULL,
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/* read multiple stream */
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NULL,
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generic_armv4_bs_rm_2,
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NULL,
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NULL,
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/* read region stream */
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NULL,
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NULL,
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NULL,
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NULL,
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/* write (single) stream */
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NULL,
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NULL,
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NULL,
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NULL,
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/* write multiple stream */
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NULL,
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generic_armv4_bs_wm_2,
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NULL,
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NULL,
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/* write region stream */
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NULL,
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NULL,
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NULL,
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NULL
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};
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bus_space_tag_t obio_tag = &econa_bs_tag;
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static int
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econa_probe(device_t dev)
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{
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device_set_desc(dev, "ECONA device bus");
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return (0);
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}
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static void
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econa_identify(driver_t *drv, device_t parent)
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{
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BUS_ADD_CHILD(parent, 0, "econaarm", 0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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extern void irq_entry(void);
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static void
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econa_add_child(device_t dev, int prio, const char *name, int unit,
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bus_addr_t addr, bus_size_t size,
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int irq0, int irq1,
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int irq2, int irq3, int irq4)
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{
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device_t kid;
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struct econa_ivar *ivar;
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kid = device_add_child_ordered(dev, prio, name, unit);
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if (kid == NULL) {
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printf("Can't add child %s%d ordered\n", name, unit);
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return;
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}
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ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (ivar == NULL) {
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device_delete_child(dev, kid);
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return;
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}
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device_set_ivars(kid, ivar);
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resource_list_init(&ivar->resources);
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if (irq0 != -1)
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bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
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if (irq1 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
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if (irq2 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
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if (irq3 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 3, irq3, 1);
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if (irq4 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 4, irq4, 1);
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if (addr != 0)
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bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
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}
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struct cpu_devs
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{
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const char *name;
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int unit;
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bus_addr_t mem_base;
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bus_size_t mem_len;
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int irq0;
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int irq1;
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int irq2;
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int irq3;
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int irq4;
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};
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struct cpu_devs econarm_devs[] =
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{
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{
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"econa_ic", 0,
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ECONA_IO_BASE + ECONA_PIC_BASE, ECONA_PIC_SIZE,
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0
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},
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{
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"system", 0,
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ECONA_IO_BASE + ECONA_SYSTEM_BASE, ECONA_SYSTEM_SIZE,
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0
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},
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{
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"uart", 0,
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ECONA_IO_BASE + ECONA_UART_BASE, ECONA_UART_SIZE,
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ECONA_IRQ_UART
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},
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{
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"timer", 0,
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ECONA_IO_BASE + ECONA_TIMER_BASE, ECONA_TIMER_SIZE,
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ECONA_IRQ_TIMER_1, ECONA_IRQ_TIMER_2
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},
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{
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"ohci", 0,
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ECONA_OHCI_VBASE, ECONA_OHCI_SIZE,
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ECONA_IRQ_OHCI
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},
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{
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"ehci", 0,
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ECONA_EHCI_VBASE, ECONA_EHCI_SIZE,
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ECONA_IRQ_EHCI
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},
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{
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"cfi", 0,
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ECONA_CFI_VBASE, ECONA_CFI_SIZE,
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0
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},
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{
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"ece", 0,
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ECONA_IO_BASE + ECONA_NET_BASE, ECONA_NET_SIZE,
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ECONA_IRQ_STATUS,
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ECONA_IRQ_TSTC, ECONA_IRQ_FSRC,
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ECONA_IRQ_TSQE, ECONA_IRQ_FSQF,
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},
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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};
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static void
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econa_cpu_add_builtin_children(device_t dev, struct econa_softc *sc)
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{
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int i;
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struct cpu_devs *walker;
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for (i = 0, walker = econarm_devs; walker->name; i++, walker++) {
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econa_add_child(dev, i, walker->name, walker->unit,
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walker->mem_base, walker->mem_len,
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walker->irq0,walker->irq1, walker->irq2,
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walker->irq3, walker->irq4);
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}
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}
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struct intc_trigger_t {
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int mode;
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int level;
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};
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static struct intc_trigger_t intc_trigger_table[] = {
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_EDGE_TRIGGER, INTC_FALLING_EDGE},
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_EDGE_TRIGGER, INTC_FALLING_EDGE},
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{INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
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{INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
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{INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
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};
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static inline uint32_t
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read_4(struct econa_softc *sc, bus_size_t off)
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{
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return bus_space_read_4(sc->ec_st, sc->ec_sys_sh, off);
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}
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static inline void
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write_4(struct econa_softc *sc, bus_size_t off, uint32_t val)
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{
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return bus_space_write_4(sc->ec_st, sc->ec_sys_sh, off, val);
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}
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static inline uint32_t
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system_read_4(struct econa_softc *sc, bus_size_t off)
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{
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return bus_space_read_4(sc->ec_st, sc->ec_system_sh, off);
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}
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static inline void
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system_write_4(struct econa_softc *sc, bus_size_t off, uint32_t val)
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{
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return bus_space_write_4(sc->ec_st, sc->ec_system_sh, off, val);
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}
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static inline void
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econa_set_irq_mode(struct econa_softc * sc, unsigned int irq,
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unsigned int mode)
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{
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unsigned int val;
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if ((mode != INTC_LEVEL_TRIGGER) && (mode != INTC_EDGE_TRIGGER))
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return;
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val = read_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET);
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if (mode == INTC_LEVEL_TRIGGER) {
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if (val & (1UL << irq)) {
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val &= ~(1UL << irq);
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write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET,
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val);
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}
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} else {
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if (!(val & (1UL << irq))) {
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val |= (1UL << irq);
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write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET,
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val);
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}
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}
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}
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/*
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* Configure interrupt trigger level to be Active High/Low
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* or Rising/Falling Edge
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*/
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static inline void
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econa_set_irq_level(struct econa_softc * sc,
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unsigned int irq, unsigned int level)
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{
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unsigned int val;
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if ((level != INTC_ACTIVE_HIGH) &&
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(level != INTC_ACTIVE_LOW) &&
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(level != INTC_RISING_EDGE) &&
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(level != INTC_FALLING_EDGE)) {
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return;
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}
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val = read_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET);
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if ((level == INTC_ACTIVE_HIGH) || (level == INTC_RISING_EDGE)) {
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if (val & (1UL << irq)) {
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val &= ~(1UL << irq);
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write_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET,
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val);
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}
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} else {
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if (!(val & (1UL << irq))) {
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val |= (1UL << irq);
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write_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET,
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val);
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}
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}
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}
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static void
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get_system_clock(void)
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{
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uint32_t sclock = system_read_4(econa_softc, SYSTEM_CLOCK);
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sclock = (sclock >> 6) & 0x03;
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switch (sclock) {
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case 0:
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CPU_clock = 175000000;
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break;
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case 1:
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CPU_clock = 200000000;
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break;
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case 2:
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CPU_clock = 225000000;
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break;
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case 3:
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CPU_clock = 250000000;
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break;
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}
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AHB_clock = CPU_clock >> 1;
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APB_clock = AHB_clock >> 1;
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}
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static int
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econa_attach(device_t dev)
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{
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struct econa_softc *sc = device_get_softc(dev);
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int i;
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econa_softc = sc;
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sc->ec_st = &econa_bs_tag;
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sc->ec_sh = ECONA_IO_BASE;
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sc->dev = dev;
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if (bus_space_subregion(sc->ec_st, sc->ec_sh, ECONA_PIC_BASE,
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ECONA_PIC_SIZE, &sc->ec_sys_sh) != 0)
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panic("Unable to map IRQ registers");
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if (bus_space_subregion(sc->ec_st, sc->ec_sh, ECONA_SYSTEM_BASE,
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ECONA_SYSTEM_SIZE, &sc->ec_system_sh) != 0)
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panic("Unable to map IRQ registers");
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sc->ec_irq_rman.rm_type = RMAN_ARRAY;
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sc->ec_irq_rman.rm_descr = "ECONA IRQs";
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sc->ec_mem_rman.rm_type = RMAN_ARRAY;
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sc->ec_mem_rman.rm_descr = "ECONA Memory";
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if (rman_init(&sc->ec_irq_rman) != 0 ||
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rman_manage_region(&sc->ec_irq_rman, 0, 31) != 0)
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panic("econa_attach: failed to set up IRQ rman");
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if (rman_init(&sc->ec_mem_rman) != 0 ||
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rman_manage_region(&sc->ec_mem_rman, 0,
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~0) != 0)
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panic("econa_attach: failed to set up memory rman");
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write_4(sc, INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET, 0xffffffff);
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write_4(sc, INTC_INTERRUPT_MASK_REG_OFFSET, 0xffffffff);
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write_4(sc, INTC_FIQ_MODE_SELECT_REG_OFFSET, 0);
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/*initialize irq*/
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for (i = 0; i < 32; i++) {
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if (intc_trigger_table[i].mode != INTC_TRIGGER_UNKNOWN) {
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econa_set_irq_mode(sc,i, intc_trigger_table[i].mode);
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econa_set_irq_level(sc, i, intc_trigger_table[i].level);
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}
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}
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get_system_clock();
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econa_cpu_add_builtin_children(dev, sc);
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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enable_interrupts(I32_bit | F32_bit);
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return (0);
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}
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static struct resource *
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econa_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct econa_softc *sc = device_get_softc(dev);
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struct resource_list_entry *rle;
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struct econa_ivar *ivar = device_get_ivars(child);
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|
struct resource_list *rl = &ivar->resources;
|
|
|
|
if (device_get_parent(child) != dev)
|
|
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
type, rid, start, end, count, flags));
|
|
|
|
rle = resource_list_find(rl, type, *rid);
|
|
if (rle == NULL) {
|
|
return (NULL);
|
|
}
|
|
if (rle->res)
|
|
panic("Resource rid %d type %d already in use", *rid, type);
|
|
if (start == 0UL && end == ~0UL) {
|
|
start = rle->start;
|
|
count = ulmax(count, rle->count);
|
|
end = ulmax(rle->end, start + count - 1);
|
|
}
|
|
switch (type)
|
|
{
|
|
case SYS_RES_IRQ:
|
|
rle->res = rman_reserve_resource(&sc->ec_irq_rman,
|
|
start, end, count, flags, child);
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rle->res = rman_reserve_resource(&sc->ec_mem_rman,
|
|
start, end, count, flags, child);
|
|
if (rle->res != NULL) {
|
|
rman_set_bustag(rle->res, &econa_bs_tag);
|
|
rman_set_bushandle(rle->res, start);
|
|
}
|
|
break;
|
|
}
|
|
if (rle->res) {
|
|
rle->start = rman_get_start(rle->res);
|
|
rle->end = rman_get_end(rle->res);
|
|
rle->count = count;
|
|
rman_set_rid(rle->res, *rid);
|
|
}
|
|
return (rle->res);
|
|
}
|
|
|
|
static struct resource_list *
|
|
econa_get_resource_list(device_t dev, device_t child)
|
|
{
|
|
struct econa_ivar *ivar;
|
|
ivar = device_get_ivars(child);
|
|
return (&(ivar->resources));
|
|
}
|
|
|
|
static int
|
|
econa_release_resource(device_t dev, device_t child, int type,
|
|
int rid, struct resource *r)
|
|
{
|
|
struct resource_list *rl;
|
|
struct resource_list_entry *rle;
|
|
|
|
rl = econa_get_resource_list(dev, child);
|
|
if (rl == NULL)
|
|
return (EINVAL);
|
|
rle = resource_list_find(rl, type, rid);
|
|
if (rle == NULL)
|
|
return (EINVAL);
|
|
rman_release_resource(r);
|
|
rle->res = NULL;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
econa_setup_intr(device_t dev, device_t child,
|
|
struct resource *ires, int flags, driver_filter_t *filt,
|
|
driver_intr_t *intr, void *arg, void **cookiep)
|
|
{
|
|
|
|
if (rman_get_start(ires) == ECONA_IRQ_SYSTEM && filt == NULL)
|
|
panic("All system interrupt ISRs must be FILTER");
|
|
|
|
BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
|
|
intr, arg, cookiep);
|
|
|
|
arm_unmask_irq(rman_get_start(ires));
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
econa_teardown_intr(device_t dev, device_t child, struct resource *res,
|
|
void *cookie)
|
|
{
|
|
|
|
return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
|
|
}
|
|
|
|
static int
|
|
econa_activate_resource(device_t bus, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
|
|
return (rman_activate_resource(r));
|
|
}
|
|
|
|
static int
|
|
econa_print_child(device_t dev, device_t child)
|
|
{
|
|
struct econa_ivar *ivars;
|
|
struct resource_list *rl;
|
|
int retval = 0;
|
|
|
|
ivars = device_get_ivars(child);
|
|
rl = &ivars->resources;
|
|
|
|
retval += bus_print_child_header(dev, child);
|
|
|
|
retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
|
|
retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
|
|
retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
|
|
if (device_get_flags(dev))
|
|
retval += printf(" flags %#x", device_get_flags(dev));
|
|
|
|
retval += bus_print_child_footer(dev, child);
|
|
|
|
return (retval);
|
|
}
|
|
|
|
void
|
|
arm_mask_irq(uintptr_t nb)
|
|
{
|
|
unsigned int value;
|
|
|
|
value = read_4(econa_softc,INTC_INTERRUPT_MASK_REG_OFFSET) | 1<<nb;
|
|
write_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET, value);
|
|
}
|
|
|
|
void
|
|
arm_unmask_irq(uintptr_t nb)
|
|
{
|
|
unsigned int value;
|
|
|
|
value = read_4(econa_softc,
|
|
INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET) | (1 << nb);
|
|
write_4(econa_softc,
|
|
INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET, value);
|
|
value = read_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET)& ~(1 << nb);
|
|
write_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET, value);
|
|
}
|
|
|
|
int
|
|
arm_get_next_irq(int x)
|
|
{
|
|
int irq;
|
|
|
|
irq = read_4(econa_softc, INTC_INTERRUPT_STATUS_REG_OFFSET) &
|
|
~(read_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET));
|
|
|
|
if (irq!=0) {
|
|
return (ffs(irq) - 1);
|
|
}
|
|
|
|
return (-1);
|
|
}
|
|
|
|
void
|
|
cpu_reset(void)
|
|
{
|
|
uint32_t control;
|
|
|
|
control = system_read_4(econa_softc, RESET_CONTROL);
|
|
control |= GLOBAL_RESET;
|
|
system_write_4(econa_softc, RESET_CONTROL, control);
|
|
control = system_read_4(econa_softc, RESET_CONTROL);
|
|
control &= (~(GLOBAL_RESET));
|
|
system_write_4(econa_softc, RESET_CONTROL, control);
|
|
while (1);
|
|
}
|
|
|
|
|
|
|
|
void
|
|
power_on_network_interface(void)
|
|
{
|
|
uint32_t cfg_reg;
|
|
int ii;
|
|
|
|
cfg_reg = system_read_4(econa_softc, RESET_CONTROL);
|
|
cfg_reg |= NET_INTERFACE_RESET;
|
|
/* set reset bit to HIGH active; */
|
|
system_write_4(econa_softc, RESET_CONTROL, cfg_reg);
|
|
|
|
/*pulse delay */
|
|
for (ii = 0; ii < 0xFFF; ii++)
|
|
DELAY(100);
|
|
/* set reset bit to LOW active; */
|
|
cfg_reg = system_read_4(econa_softc, RESET_CONTROL);
|
|
cfg_reg &= ~(NET_INTERFACE_RESET);
|
|
system_write_4(econa_softc, RESET_CONTROL, cfg_reg);
|
|
|
|
/*pulse delay */
|
|
for (ii = 0; ii < 0xFFF; ii++)
|
|
DELAY(100);
|
|
cfg_reg = system_read_4(econa_softc, RESET_CONTROL);
|
|
cfg_reg |= NET_INTERFACE_RESET;
|
|
/* set reset bit to HIGH active; */
|
|
system_write_4(econa_softc, RESET_CONTROL, cfg_reg);
|
|
}
|
|
|
|
unsigned int
|
|
get_tclk(void)
|
|
{
|
|
|
|
return CPU_clock;
|
|
}
|
|
|
|
static device_method_t econa_methods[] = {
|
|
DEVMETHOD(device_probe, econa_probe),
|
|
DEVMETHOD(device_attach, econa_attach),
|
|
DEVMETHOD(device_identify, econa_identify),
|
|
DEVMETHOD(bus_alloc_resource, econa_alloc_resource),
|
|
DEVMETHOD(bus_setup_intr, econa_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, econa_teardown_intr),
|
|
DEVMETHOD(bus_activate_resource, econa_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_get_resource_list, econa_get_resource_list),
|
|
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
|
|
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
|
|
DEVMETHOD(bus_release_resource, econa_release_resource),
|
|
DEVMETHOD(bus_print_child, econa_print_child),
|
|
{0, 0},
|
|
};
|
|
|
|
static driver_t econa_driver = {
|
|
"econaarm",
|
|
econa_methods,
|
|
sizeof(struct econa_softc),
|
|
};
|
|
static devclass_t econa_devclass;
|
|
|
|
DRIVER_MODULE(econaarm, nexus, econa_driver, econa_devclass, 0, 0);
|