340 lines
9.4 KiB
C
340 lines
9.4 KiB
C
/*-
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* Copyright (c) 2006 Kip Macy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_HYPERVISORVAR_H_
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#define _MACHINE_HYPERVISORVAR_H_
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/*
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* Trap types
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*/
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#define FAST_TRAP 0x80 /* Function # in %o5 */
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#define CPU_TICK_NPT 0x81
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#define CPU_STICK_NPT 0x82
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#define MMU_MAP_ADDR 0x83
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#define MMU_UNMAP_ADDR 0x84
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#define TTRACE_ADDENTRY 0x85
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#define CORE_TRAP 0xff
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/*
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* Status returns in %o0.
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*/
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#define H_EOK 0 /* Successful return */
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#define H_ENOCPU 1 /* Invalid CPU id */
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#define H_ENORADDR 2 /* Invalid real address */
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#define H_ENOINTR 3 /* Invalid interrupt id */
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#define H_EBADPGSZ 4 /* Invalid pagesize encoding */
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#define H_EBADTSB 5 /* Invalid TSB description */
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#define H_EINVAL 6 /* Invalid argument */
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#define H_EBADTRAP 7 /* Invalid function number */
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#define H_EBADALIGN 8 /* Invalid address alignment */
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#define H_EWOULDBLOCK 9 /* Cannot complete operation */
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/* without blocking */
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#define H_ENOACCESS 10 /* No access to resource */
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#define H_EIO 11 /* I/O error */
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#define H_ECPUERROR 12 /* CPU is in error state */
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#define H_ENOTSUPPORTED 13 /* Function not supported */
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#define H_ENOMAP 14 /* Mapping is not valid, */
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/* no translation exists */
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#define H_ETOOMANY 15 /* Too many items specified / limit reached */
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#define H_ECHANNEL 16 /* Invalid LDC channel */
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#define H_BREAK -1 /* Console Break */
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#define H_HUP -2 /* Console Break */
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/*
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* Mondo CPU ID argument processing.
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*/
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#define HV_SEND_MONDO_ENTRYDONE 0xffff
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/*
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* Function numbers for CORE_TRAP.
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*/
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#define API_SET_VERSION 0x00
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#define API_PUTCHAR 0x01
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#define API_EXIT 0x02
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#define API_GET_VERSION 0x03
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/*
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* Function numbers for FAST_TRAP.
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*/
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#define MACH_EXIT 0x00
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#define MACH_DESC 0x01
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#define MACH_SET_SOFT_STATE 0x03
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#define MACH_GET_SOFT_STATE 0x04
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#define MACH_WATCHDOG 0x05
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#define CPU_START 0x10
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#define CPU_STOP 0x11
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#define CPU_YIELD 0x12
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#define CPU_QCONF 0x14
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#define CPU_QINFO 0x15
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#define CPU_MYID 0x16
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#define CPU_STATE 0x17
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#define CPU_SET_RTBA 0x18
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#define CPU_GET_RTBA 0x19
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#define MMU_TSB_CTX0 0x20
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#define MMU_TSB_CTXNON0 0x21
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#define MMU_DEMAP_PAGE 0x22
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#define MMU_DEMAP_CTX 0x23
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#define MMU_DEMAP_ALL 0x24
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#define MAP_PERM_ADDR 0x25
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#define MMU_MAP_PERM_ADDR 0x26
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#define MMU_ENABLE 0x27
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#define MMU_UNMAP_PERM_ADDR 0x28
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#define MMU_TSB_CTX0_INFO 0x29
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#define MMU_TSB_CTXNON0_INFO 0x2a
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#define MMU_FAULT_AREA_INFO 0x2b
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/*
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* Bits for MMU functions flags argument:
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* arg3 of MMU_MAP_ADDR
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* arg3 of MMU_DEMAP_CTX
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* arg2 of MMU_DEMAP_ALL
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*/
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#define MAP_DTLB 0x1
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#define MAP_ITLB 0x2
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#define MEM_SCRUB 0x31
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#define MEM_SYNC 0x32
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#define CPU_MONDO_SEND 0x42
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#define TOD_GET 0x50
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#define TOD_SET 0x51
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#define CONS_GETCHAR 0x60
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#define CONS_PUTCHAR 0x61
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#define CONS_READ 0x62
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#define CONS_WRITE 0x63
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#define SVC_SEND 0x80
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#define SVC_RECV 0x81
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#define SVC_GETSTATUS 0x82
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#define SVC_SETSTATUS 0x83
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#define SVC_CLRSTATUS 0x84
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#define TTRACE_BUF_CONF 0x90
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#define TTRACE_BUF_INFO 0x91
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#define TTRACE_ENABLE 0x92
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#define TTRACE_FREEZE 0x93
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#define DUMP_BUF_UPDATE 0x94
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#define DUMP_BUF_INFO 0x95
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#define INTR_DEVINO2SYSINO 0xa0
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#define INTR_GETENABLED 0xa1
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#define INTR_SETENABLED 0xa2
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#define INTR_GETSTATE 0xa3
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#define INTR_SETSTATE 0xa4
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#define INTR_GETTARGET 0xa5
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#define INTR_SETTARGET 0xa6
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#define PCI_IOMMU_MAP 0xb0
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#define PCI_IOMMU_DEMAP 0xb1
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#define PCI_IOMMU_GETMAP 0xb2
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#define PCI_IOMMU_GETBYPASS 0xb3
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#define PCI_CONFIG_GET 0xb4
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#define PCI_CONFIG_PUT 0xb5
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#define PCI_PEEK 0xb6
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#define PCI_POKE 0xb7
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#define PCI_DMA_SYNC 0xb8
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#define PCI_MSIQ_CONF 0xc0
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#define PCI_MSIQ_INFO 0xc1
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#define PCI_MSIQ_GETVALID 0xc2
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#define PCI_MSIQ_SETVALID 0xc3
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#define PCI_MSIQ_GETSTATE 0xc4
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#define PCI_MSIQ_SETSTATE 0xc5
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#define PCI_MSIQ_GETHEAD 0xc6
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#define PCI_MSIQ_SETHEAD 0xc7
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#define PCI_MSIQ_GETTAIL 0xc8
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#define PCI_MSI_GETVALID 0xc9
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#define PCI_MSI_SETVALID 0xca
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#define PCI_MSI_GETMSIQ 0xcb
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#define PCI_MSI_SETMSIQ 0xcc
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#define PCI_MSI_GETSTATE 0xcd
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#define PCI_MSI_SETSTATE 0xce
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#define PCI_MSG_GETMSIQ 0xd0
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#define PCI_MSG_SETMSIQ 0xd1
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#define PCI_MSG_GETVALID 0xd2
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#define PCI_MSG_SETVALID 0xd3
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#define LDC_TX_QCONF 0xe0
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#define LDC_TX_QINFO 0xe1
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#define LDC_TX_GET_STATE 0xe2
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#define LDC_TX_SET_QTAIL 0xe3
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#define LDC_RX_QCONF 0xe4
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#define LDC_RX_QINFO 0xe5
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#define LDC_RX_GET_STATE 0xe6
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#define LDC_RX_SET_QHEAD 0xe7
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#define LDC_SET_MAP_TABLE 0xea
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#define LDC_GET_MAP_TABLE 0xeb
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#define LDC_COPY 0xec
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#define LDC_MAPIN 0xed
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#define LDC_UNMAP 0xee
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#define LDC_REVOKE 0xef
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#define SIM_READ 0xf0
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#define SIM_WRITE 0xf1
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#define NIAGARA_GET_PERFREG 0x100
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#define NIAGARA_SET_PERFREG 0x101
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#define NIAGARA_MMUSTAT_CONF 0x102
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#define NIAGARA_MMUSTAT_INFO 0x103
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/*
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* Interrupt state manipulation definitions.
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*/
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#define HV_INTR_IDLE_STATE 0
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#define HV_INTR_RECEIVED_STATE 1
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#define HV_INTR_DELIVERED_STATE 2
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#define HV_INTR_NOTVALID 0
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#define HV_INTR_VALID 1
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#ifndef LOCORE
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#ifdef SET_MMU_STATS
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#ifndef TTE4V_NPGSZ
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#define TTE4V_NPGSZ 8
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#endif /* TTE4V_NPGSZ */
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/*
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* MMU statistics structure for MMU_STAT_AREA
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*/
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struct mmu_stat_one {
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uint64_t hit_ctx0[TTE4V_NPGSZ];
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uint64_t hit_ctxn0[TTE4V_NPGSZ];
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uint64_t tsb_miss;
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uint64_t tlb_miss; /* miss, no TSB set */
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uint64_t map_ctx0[TTE4V_NPGSZ];
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uint64_t map_ctxn0[TTE4V_NPGSZ];
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};
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struct mmu_stat {
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struct mmu_stat_one immu_stat;
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struct mmu_stat_one dmmu_stat;
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uint64_t set_ctx0;
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uint64_t set_ctxn0;
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};
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#endif /* SET_MMU_STATS */
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#endif /* _ASM */
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/*
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* CPU States
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*/
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#define CPU_STATE_INVALID 0x0
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#define CPU_STATE_IDLE 0x1 /* cpu not started */
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#define CPU_STATE_GUEST 0x2 /* cpu running guest code */
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#define CPU_STATE_ERROR 0x3 /* cpu is in the error state */
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#define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */
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/*
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* MMU fault status area
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*/
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#define MMFSA_TYPE_ 0x00 /* fault type */
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#define MMFSA_ADDR_ 0x08 /* fault address */
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#define MMFSA_CTX_ 0x10 /* fault context */
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#define MMFSA_I_ 0x00 /* start of fields for I */
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#define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */
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#define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */
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#define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */
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#define MMFSA_D_ 0x40 /* start of fields for D */
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#define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */
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#define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */
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#define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */
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#define MMFSA_F_FMISS 1 /* fast miss */
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#define MMFSA_F_FPROT 2 /* fast protection */
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#define MMFSA_F_MISS 3 /* mmu miss */
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#define MMFSA_F_INVRA 4 /* invalid RA */
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#define MMFSA_F_PRIV 5 /* privilege violation */
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#define MMFSA_F_PROT 6 /* protection violation */
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#define MMFSA_F_NFO 7 /* NFO access */
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#define MMFSA_F_SOPG 8 /* so page */
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#define MMFSA_F_INVVA 9 /* invalid VA */
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#define MMFSA_F_INVASI 10 /* invalid ASI */
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#define MMFSA_F_NCATM 11 /* non-cacheable atomic */
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#define MMFSA_F_PRVACT 12 /* privileged action */
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#define MMFSA_F_WPT 13 /* watchpoint hit */
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#define MMFSA_F_UNALIGN 14 /* unaligned access */
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#define MMFSA_F_INVPGSZ 15 /* invalid page size */
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#define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */
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/*
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* MMU fault status - MMFSA_IFS and MMFSA_DFS
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*/
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#define MMFS_FV 0x00000001
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#define MMFS_OW 0x00000002
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#define MMFS_W 0x00000004
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#define MMFS_PR 0x00000008
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#define MMFS_CT 0x00000030
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#define MMFS_E 0x00000040
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#define MMFS_FT 0x00003f80
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#define MMFS_ME 0x00004000
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#define MMFS_TM 0x00008000
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#define MMFS_ASI 0x00ff0000
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#define MMFS_NF 0x01000000
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/*
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* DMA sync parameter definitions
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*/
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#define HVIO_DMA_SYNC_DIR_TO_DEV 0x01
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#define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02
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#ifdef SIMULATOR
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#define MAGIC_TRAP_ON ta 0x77
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#define MAGIC_TRAP_OFF ta 0x78
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#define MAGIC_EXIT ta 0x71
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#else
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#define MAGIC_TRAP_ON nop
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#define MAGIC_TRAP_OFF nop
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#define MAGIC_EXIT nop
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#endif
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#endif /*_MACHINE_HYPERVISORVAR_H_ */
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