cfc8861b06
- Put all clock and control unit driver in BUS_PASS_RESOURCE except for the DE2 CCU as it needs the main CCU to be available. - Use BUS_PASS_CPU for a20_cpu_cfg as it makes more sense. - For aw_syscon use SCHEDULER pass as we need it early for drivers that attach in BUS_PASS_SUPPORTDEV - For the rest we can use BUS_PASS_SUPPORTDEV
418 lines
9.8 KiB
C
418 lines
9.8 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner secure ID controller
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/endian.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/allwinner/aw_sid.h>
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#include "nvmem_if.h"
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/*
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* Starting at least from sun8iw6 (A83T) EFUSE starts at 0x200
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* There is 3 registers in the low area to read/write protected EFUSE.
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*/
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#define SID_PRCTL 0x40
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#define SID_PRCTL_OFFSET_MASK 0xff
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#define SID_PRCTL_OFFSET(n) (((n) & SID_PRCTL_OFFSET_MASK) << 16)
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#define SID_PRCTL_LOCK (0xac << 8)
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#define SID_PRCTL_READ (0x01 << 1)
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#define SID_PRCTL_WRITE (0x01 << 0)
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#define SID_PRKEY 0x50
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#define SID_RDKEY 0x60
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#define EFUSE_OFFSET 0x200
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#define EFUSE_NAME_SIZE 32
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#define EFUSE_DESC_SIZE 64
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struct aw_sid_efuse {
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char name[EFUSE_NAME_SIZE];
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char desc[EFUSE_DESC_SIZE];
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bus_size_t base;
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bus_size_t offset;
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uint32_t size;
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enum aw_sid_fuse_id id;
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bool public;
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};
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static struct aw_sid_efuse a10_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.offset = 0x0,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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};
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static struct aw_sid_efuse a64_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 6,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = true,
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},
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};
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static struct aw_sid_efuse a83t_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 8,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = true,
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},
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};
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static struct aw_sid_efuse h3_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 2,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = false,
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},
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};
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static struct aw_sid_efuse h5_efuses[] = {
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{
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.name = "rootkey",
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.desc = "Root Key or ChipID",
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.base = EFUSE_OFFSET,
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.offset = 0x00,
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.size = 16,
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.id = AW_SID_FUSE_ROOTKEY,
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.public = true,
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},
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{
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.name = "ths-calib",
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.desc = "Thermal Sensor Calibration Data",
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.base = EFUSE_OFFSET,
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.offset = 0x34,
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.size = 4,
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.id = AW_SID_FUSE_THSSENSOR,
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.public = true,
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},
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};
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struct aw_sid_conf {
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struct aw_sid_efuse *efuses;
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size_t nfuses;
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};
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static const struct aw_sid_conf a10_conf = {
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.efuses = a10_efuses,
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.nfuses = nitems(a10_efuses),
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};
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static const struct aw_sid_conf a20_conf = {
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.efuses = a10_efuses,
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.nfuses = nitems(a10_efuses),
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};
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static const struct aw_sid_conf a64_conf = {
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.efuses = a64_efuses,
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.nfuses = nitems(a64_efuses),
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};
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static const struct aw_sid_conf a83t_conf = {
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.efuses = a83t_efuses,
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.nfuses = nitems(a83t_efuses),
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};
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static const struct aw_sid_conf h3_conf = {
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.efuses = h3_efuses,
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.nfuses = nitems(h3_efuses),
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};
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static const struct aw_sid_conf h5_conf = {
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.efuses = h5_efuses,
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.nfuses = nitems(h5_efuses),
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-sid", (uintptr_t)&a10_conf},
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{ "allwinner,sun7i-a20-sid", (uintptr_t)&a20_conf},
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{ "allwinner,sun50i-a64-sid", (uintptr_t)&a64_conf},
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{ "allwinner,sun8i-a83t-sid", (uintptr_t)&a83t_conf},
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{ "allwinner,sun8i-h3-sid", (uintptr_t)&h3_conf},
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{ "allwinner,sun50i-h5-sid", (uintptr_t)&h5_conf},
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{ NULL, 0 }
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};
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struct aw_sid_softc {
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device_t sid_dev;
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struct resource *res;
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struct aw_sid_conf *sid_conf;
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struct mtx prctl_mtx;
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};
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static struct aw_sid_softc *aw_sid_sc;
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static struct resource_spec aw_sid_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define RD1(sc, reg) bus_read_1((sc)->res, (reg))
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#define RD4(sc, reg) bus_read_4((sc)->res, (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
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static int aw_sid_sysctl(SYSCTL_HANDLER_ARGS);
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static int
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aw_sid_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner Secure ID Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_sid_attach(device_t dev)
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{
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struct aw_sid_softc *sc;
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phandle_t node;
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int i;
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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sc->sid_dev = dev;
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if (bus_alloc_resources(dev, aw_sid_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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mtx_init(&sc->prctl_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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sc->sid_conf = (struct aw_sid_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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aw_sid_sc = sc;
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/* Register ourself so device can resolve who we are */
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OF_device_register_xref(OF_xref_from_node(node), dev);
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for (i = 0; i < sc->sid_conf->nfuses ;i++) {\
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SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
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OID_AUTO, sc->sid_conf->efuses[i].name,
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CTLTYPE_STRING | CTLFLAG_RD,
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dev, sc->sid_conf->efuses[i].id, aw_sid_sysctl,
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"A", sc->sid_conf->efuses[i].desc);
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}
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return (0);
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}
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int
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aw_sid_get_fuse(enum aw_sid_fuse_id id, uint8_t *out, uint32_t *size)
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{
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struct aw_sid_softc *sc;
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uint32_t val;
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int i, j;
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sc = aw_sid_sc;
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if (sc == NULL)
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return (ENXIO);
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for (i = 0; i < sc->sid_conf->nfuses; i++)
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if (id == sc->sid_conf->efuses[i].id)
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break;
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if (i == sc->sid_conf->nfuses)
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return (ENOENT);
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if (*size != sc->sid_conf->efuses[i].size) {
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*size = sc->sid_conf->efuses[i].size;
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return (ENOMEM);
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}
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if (out == NULL)
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return (ENOMEM);
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if (sc->sid_conf->efuses[i].public == false)
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mtx_lock(&sc->prctl_mtx);
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for (j = 0; j < sc->sid_conf->efuses[i].size; j += 4) {
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if (sc->sid_conf->efuses[i].public == false) {
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val = SID_PRCTL_OFFSET(sc->sid_conf->efuses[i].offset + j) |
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SID_PRCTL_LOCK |
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SID_PRCTL_READ;
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WR4(sc, SID_PRCTL, val);
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/* Read bit will be cleared once read has concluded */
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while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ)
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continue;
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val = RD4(sc, SID_RDKEY);
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} else
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val = RD4(sc, sc->sid_conf->efuses[i].base +
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sc->sid_conf->efuses[i].offset + j);
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out[j] = val & 0xFF;
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if (j + 1 < *size)
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out[j + 1] = (val & 0xFF00) >> 8;
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if (j + 2 < *size)
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out[j + 2] = (val & 0xFF0000) >> 16;
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if (j + 3 < *size)
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out[j + 3] = (val & 0xFF000000) >> 24;
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}
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if (sc->sid_conf->efuses[i].public == false)
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mtx_unlock(&sc->prctl_mtx);
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return (0);
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}
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static int
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aw_sid_read(device_t dev, uint32_t offset, uint32_t size, uint8_t *buffer)
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{
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struct aw_sid_softc *sc;
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enum aw_sid_fuse_id fuse_id = 0;
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int i;
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sc = device_get_softc(dev);
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for (i = 0; i < sc->sid_conf->nfuses; i++)
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if (offset == (sc->sid_conf->efuses[i].base +
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sc->sid_conf->efuses[i].offset)) {
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fuse_id = sc->sid_conf->efuses[i].id;
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break;
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}
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if (fuse_id == 0)
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return (ENOENT);
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return (aw_sid_get_fuse(fuse_id, buffer, &size));
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}
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static int
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aw_sid_sysctl(SYSCTL_HANDLER_ARGS)
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{
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struct aw_sid_softc *sc;
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device_t dev = arg1;
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enum aw_sid_fuse_id fuse = arg2;
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uint8_t data[32];
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char out[128];
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uint32_t size;
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int ret, i;
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sc = device_get_softc(dev);
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/* Get the size of the efuse data */
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size = 0;
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aw_sid_get_fuse(fuse, NULL, &size);
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/* We now have the real size */
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ret = aw_sid_get_fuse(fuse, data, &size);
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if (ret != 0) {
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device_printf(dev, "Cannot get fuse id %d: %d\n", fuse, ret);
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return (ENOENT);
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}
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for (i = 0; i < size; i++)
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snprintf(out + (i * 2), sizeof(out) - (i * 2),
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"%.2x", data[i]);
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return sysctl_handle_string(oidp, out, sizeof(out), req);
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}
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static device_method_t aw_sid_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_sid_probe),
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DEVMETHOD(device_attach, aw_sid_attach),
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/* NVMEM interface */
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DEVMETHOD(nvmem_read, aw_sid_read),
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DEVMETHOD_END
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};
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static driver_t aw_sid_driver = {
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"aw_sid",
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aw_sid_methods,
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sizeof(struct aw_sid_softc),
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};
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static devclass_t aw_sid_devclass;
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EARLY_DRIVER_MODULE(aw_sid, simplebus, aw_sid_driver, aw_sid_devclass, 0, 0,
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BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_FIRST);
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MODULE_VERSION(aw_sid, 1);
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SIMPLEBUS_PNP_INFO(compat_data);
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