Marcel Moolenaar 7a1f364c7d On Montecito processors, the instruction cache is in fact not ...

coherent with the data caches. Implement a quick fix to allow
us to boot on Montecito, while I'm working on a better fix in
the mean time.

Commit made on Montecito-based Itanium...

2008-02-14 18:46:50 +00:00

..

acpica

Catch up with ACPI-CA 20070320 import.

2007-03-22 18:16:43 +00:00

compile

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conf

Add COMPAT_FREEBSD7 and enable it in configs that have COMPAT_FREEBSD6.

2008-01-07 21:40:11 +00:00

disasm

Fix disassembly of the invala, itc, itr and hint instructions

2007-10-16 02:49:40 +00:00

ia32

Rework the PCPU_* (MD) interface:

2007-06-04 21:38:48 +00:00

ia64

On Montecito processors, the instruction cache is in fact not

2008-02-14 18:46:50 +00:00

include

Allocate a stack for thread0 and switch to it before calling

2008-02-04 02:21:33 +00:00

isa

dma_tag is a static structure. Testing for it being a NULL pointer

2007-07-09 04:58:16 +00:00

pci

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