7da240d003
giving astpending two flag bits. A cmpl $0 had to turn into a bit test. Many thanks to: Alain Thivillon <Alain.Thivillon@hsc.fr>
324 lines
8.6 KiB
ArmAsm
324 lines
8.6 KiB
ArmAsm
/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ipl.s
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*
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* $FreeBSD$
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*/
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/*
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* AT/386
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* Vector interrupt control section
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*
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* cpl - Current interrupt disable mask
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* *_imask - Interrupt masks for various spl*() functions
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* ipending - Pending interrupts (set when a masked interrupt occurs)
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*/
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.data
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ALIGN_DATA
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/* current priority (all off) */
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.globl _cpl
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_cpl: .long HWI_MASK | SWI_MASK
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.globl _tty_imask
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_tty_imask: .long SWI_TTY_MASK
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.globl _bio_imask
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_bio_imask: .long SWI_CLOCK_MASK | SWI_CAMBIO_MASK
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.globl _net_imask
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_net_imask: .long SWI_NET_MASK | SWI_CAMNET_MASK
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.globl _cam_imask
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_cam_imask: .long SWI_CAMBIO_MASK | SWI_CAMNET_MASK
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.globl _soft_imask
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_soft_imask: .long SWI_MASK
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.globl _softnet_imask
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_softnet_imask: .long SWI_NET_MASK
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.globl _softtty_imask
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_softtty_imask: .long SWI_TTY_MASK
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/* pending interrupts blocked by splxxx() */
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.globl _ipending
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_ipending: .long 0
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/* set with bits for which queue to service */
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.globl _netisr
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_netisr: .long 0
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.globl _netisrs
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_netisrs:
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.text
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/*
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* Handle return from interrupts, traps and syscalls.
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*/
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SUPERALIGN_TEXT
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.type _doreti,@function
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_doreti:
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FAKE_MCOUNT(_bintr) /* init "from" _bintr -> _doreti */
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addl $4,%esp /* discard unit number */
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popl %eax /* cpl or cml to restore */
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doreti_next:
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/*
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* Check for pending HWIs and SWIs atomically with restoring cpl
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* and exiting. The check has to be atomic with exiting to stop
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* (ipending & ~cpl) changing from zero to nonzero while we're
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* looking at it (this wouldn't be fatal but it would increase
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* interrupt latency). Restoring cpl has to be atomic with exiting
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* so that the stack cannot pile up (the nesting level of interrupt
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* handlers is limited by the number of bits in cpl).
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*/
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#ifdef SMP
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cli /* early to prevent INT deadlock */
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doreti_next2:
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#endif
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movl %eax,%ecx
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notl %ecx /* set bit = unmasked level */
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#ifndef SMP
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cli
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#endif
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andl _ipending,%ecx /* set bit = unmasked pending INT */
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jne doreti_unpend
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movl %eax,_cpl
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decb _intr_nesting_level
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/* Check for ASTs that can be handled now. */
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testl $AST_PENDING,_astpending
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je doreti_exit
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testb $SEL_RPL_MASK,TF_CS(%esp)
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jne doreti_ast
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testl $PSL_VM,TF_EFLAGS(%esp)
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je doreti_exit
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cmpl $1,_in_vm86call
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jne doreti_ast
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/*
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* doreti_exit - release MP lock, pop registers, iret.
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*
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* Note that the syscall trap shotcuts to doreti_syscall_ret.
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* The segment register pop is a special case, since it may
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* fault if (for example) a sigreturn specifies bad segment
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* registers. The fault is handled in trap.c
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*/
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doreti_exit:
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MEXITCOUNT
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#ifdef SMP
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/* release the kernel lock */
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movl $_mp_lock, %edx /* GIANT_LOCK */
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call _MPrellock_edx
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#endif /* SMP */
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.globl doreti_popl_fs
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.globl doreti_syscall_ret
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doreti_syscall_ret:
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doreti_popl_fs:
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popl %fs
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.globl doreti_popl_es
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doreti_popl_es:
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popl %es
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.globl doreti_popl_ds
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doreti_popl_ds:
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popl %ds
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popal
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addl $8,%esp
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.globl doreti_iret
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doreti_iret:
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iret
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ALIGN_TEXT
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.globl doreti_iret_fault
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doreti_iret_fault:
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subl $8,%esp
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pushal
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pushl %ds
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.globl doreti_popl_ds_fault
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doreti_popl_ds_fault:
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pushl %es
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.globl doreti_popl_es_fault
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doreti_popl_es_fault:
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pushl %fs
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.globl doreti_popl_fs_fault
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doreti_popl_fs_fault:
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movl $0,TF_ERR(%esp) /* XXX should be the error code */
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movl $T_PROTFLT,TF_TRAPNO(%esp)
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jmp alltraps_with_regs_pushed
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ALIGN_TEXT
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doreti_unpend:
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/*
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* Enabling interrupts is safe because we haven't restored cpl yet.
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* %ecx contains the next probable ready interrupt (~cpl & ipending)
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*/
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#ifdef SMP
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bsfl %ecx, %ecx /* locate the next dispatchable int */
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lock
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btrl %ecx, _ipending /* is it really still pending? */
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jnc doreti_next2 /* some intr cleared memory copy */
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sti /* late to prevent INT deadlock */
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#else
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sti
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bsfl %ecx,%ecx /* slow, but not worth optimizing */
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btrl %ecx,_ipending
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jnc doreti_next /* some intr cleared memory copy */
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#endif /* SMP */
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/*
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* Execute handleable interrupt
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*
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* Set up JUMP to _ihandlers[%ecx] for HWIs.
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* Set up CALL of _ihandlers[%ecx] for SWIs.
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* This is a bit early for the SMP case - we have to push %ecx and
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* %edx, but could push only %ecx and load %edx later.
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*/
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movl _ihandlers(,%ecx,4),%edx
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cmpl $NHWI,%ecx
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jae doreti_swi /* software interrupt handling */
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cli /* else hardware int handling */
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#ifdef SMP
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movl %eax,_cpl /* same as non-smp case right now */
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#else
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movl %eax,_cpl
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#endif
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MEXITCOUNT
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#ifdef APIC_INTR_DIAGNOSTIC
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lock
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incl CNAME(apic_itrace_doreti)(,%ecx,4)
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#ifdef APIC_INTR_DIAGNOSTIC_IRQ
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cmpl $APIC_INTR_DIAGNOSTIC_IRQ,%ecx
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jne 9f
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl $APIC_ITRACE_DORETI
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call log_intr_event
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addl $4,%esp
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popl %edx
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popl %ecx
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popl %eax
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9:
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#endif
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#endif
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jmp %edx
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ALIGN_TEXT
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doreti_swi:
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pushl %eax
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/*
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* At least the SWI_CLOCK handler has to run at a possibly strictly
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* lower cpl, so we have to restore
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* all the h/w bits in cpl now and have to worry about stack growth.
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* The worst case is currently (30 Jan 1994) 2 SWI handlers nested
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* in dying interrupt frames and about 12 HWIs nested in active
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* interrupt frames. There are only 4 different SWIs and the HWI
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* and SWI masks limit the nesting further.
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*
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* The SMP case is currently the same as the non-SMP case.
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*/
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#ifdef SMP
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orl imasks(,%ecx,4), %eax /* or in imasks */
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movl %eax,_cpl /* set cpl for call */
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#else
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orl imasks(,%ecx,4),%eax
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movl %eax,_cpl
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#endif
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call %edx
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popl %eax /* cpl to restore */
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jmp doreti_next
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ALIGN_TEXT
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doreti_ast:
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andl $~AST_PENDING,_astpending
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sti
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movl $T_ASTFLT,TF_TRAPNO(%esp)
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call _trap
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subl %eax,%eax /* recover cpl|cml */
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movb $1,_intr_nesting_level /* for doreti_next to decrement */
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jmp doreti_next
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ALIGN_TEXT
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swi_net:
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MCOUNT
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bsfl _netisr,%eax
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je swi_net_done
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swi_net_more:
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btrl %eax,_netisr
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jnc swi_net_next
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call *_netisrs(,%eax,4)
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swi_net_next:
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bsfl _netisr,%eax
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jne swi_net_more
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swi_net_done:
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ret
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ALIGN_TEXT
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dummynetisr:
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MCOUNT
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ret
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/*
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* The arg is in a nonstandard place, so swi_dispatcher() can't be called
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* directly and swi_generic() can't use ENTRY() or MCOUNT.
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*/
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ALIGN_TEXT
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.globl _swi_generic
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.type _swi_generic,@function
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_swi_generic:
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pushl %ecx
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FAKE_MCOUNT(4(%esp))
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call _swi_dispatcher
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popl %ecx
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ret
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ENTRY(swi_null)
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ret
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#ifdef APIC_IO
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#include "i386/isa/apic_ipl.s"
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#else
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#include "i386/isa/icu_ipl.s"
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#endif /* APIC_IO */
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