8627141c50
Changed the fifth parameter to register_intr() from u_int mask into u_int *maskptr in preparation for new features (shared interrupts and removable devices, eg. for PCMCIA).
579 lines
14 KiB
C
579 lines
14 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.24 1994/10/04 18:39:10 ache Exp $
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*/
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/*
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* inittodr, settodr and support routines written
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* by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
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*
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* reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
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*/
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/*
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* Primitive clock interrupt routines.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <machine/frame.h>
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#include <i386/isa/icu.h>
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#include <i386/isa/isa.h>
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#include <i386/isa/rtc.h>
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#include <i386/isa/timerreg.h>
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/*
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* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
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* can use a simple formula for leap years.
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*/
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#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
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#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
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/* X-tals being what they are, it's nice to be able to fudge this one... */
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/* Note, the name changed here from XTALSPEED to TIMER_FREQ rgrimes 4/26/93 */
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#ifndef TIMER_FREQ
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#define TIMER_FREQ 1193182 /* XXX - should be in isa.h */
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#endif
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#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
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static int beeping;
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int timer0_divisor = TIMER_DIV(100); /* XXX should be hz */
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u_int timer0_prescale;
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int adjkerntz = 0; /* offset from CMOS clock */
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int disable_rtc_set = 0; /* disable resettodr() if != 0 */
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static char timer0_state = 0, timer2_state = 0;
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static char timer0_reprogram = 0;
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static void (*timer_func)() = hardclock;
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static void (*new_function)();
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static u_int new_rate;
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static u_int hardclock_divisor;
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static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
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#ifdef I586_CPU
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int pentium_mhz = 0;
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#endif
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#if 0
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void
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clkintr(struct clockframe frame)
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{
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hardclock(&frame);
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}
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#else
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void
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clkintr(struct clockframe frame)
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{
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timer_func(&frame);
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switch (timer0_state) {
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case 0:
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break;
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case 1:
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if ((timer0_prescale+=timer0_divisor) >= hardclock_divisor) {
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hardclock(&frame);
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timer0_prescale = 0;
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}
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break;
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case 2:
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disable_intr();
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outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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outb(TIMER_CNTR0, TIMER_DIV(new_rate)%256);
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outb(TIMER_CNTR0, TIMER_DIV(new_rate)/256);
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enable_intr();
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timer0_divisor = TIMER_DIV(new_rate);
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timer0_prescale = 0;
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timer_func = new_function;
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timer0_state = 1;
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break;
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case 3:
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if ((timer0_prescale+=timer0_divisor) >= hardclock_divisor) {
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hardclock(&frame);
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disable_intr();
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outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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outb(TIMER_CNTR0, TIMER_DIV(hz)%256);
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outb(TIMER_CNTR0, TIMER_DIV(hz)/256);
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enable_intr();
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timer0_divisor = TIMER_DIV(hz);
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timer0_prescale = 0;
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timer_func = hardclock;;
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timer0_state = 0;
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}
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break;
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}
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}
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#endif
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int
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acquire_timer0(int rate, void (*function)() )
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{
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if (timer0_state || !function)
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return -1;
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new_function = function;
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new_rate = rate;
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timer0_state = 2;
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return 0;
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}
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int
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acquire_timer2(int mode)
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{
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if (timer2_state)
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return -1;
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timer2_state = 1;
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outb(TIMER_MODE, TIMER_SEL2 | (mode &0x3f));
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return 0;
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}
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int
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release_timer0()
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{
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if (!timer0_state)
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return -1;
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timer0_state = 3;
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return 0;
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}
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int
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release_timer2()
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{
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if (!timer2_state)
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return -1;
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timer2_state = 0;
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outb(TIMER_MODE, TIMER_SEL2|TIMER_SQWAVE|TIMER_16BIT);
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return 0;
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}
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/*
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* This routine receives statistical clock interrupts from the RTC.
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* As explained above, these occur at 128 interrupts per second.
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* When profiling, we receive interrupts at a rate of 1024 Hz.
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*
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* This does not actually add as much overhead as it sounds, because
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* when the statistical clock is active, the hardclock driver no longer
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* needs to keep (inaccurate) statistics on its own. This decouples
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* statistics gathering from scheduling interrupts.
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*
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* The RTC chip requires that we read status register C (RTC_INTR)
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* to acknowledge an interrupt, before it will generate the next one.
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*/
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void
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rtcintr(struct clockframe frame)
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{
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u_char stat;
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stat = rtcin(RTC_INTR);
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if(stat & RTCIR_PERIOD) {
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statclock(&frame);
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}
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}
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#ifdef DEBUG
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void
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printrtc(void)
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{
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outb(IO_RTC, RTC_STATUSA);
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printf("RTC status A = %x", inb(IO_RTC+1));
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outb(IO_RTC, RTC_STATUSB);
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printf(", B = %x", inb(IO_RTC+1));
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outb(IO_RTC, RTC_INTR);
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printf(", C = %x\n", inb(IO_RTC+1));
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}
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#endif
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static int
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getit()
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{
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int high, low;
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disable_intr();
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/* select timer0 and latch counter value */
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outb(TIMER_MODE, TIMER_SEL0);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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enable_intr();
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return ((high << 8) | low);
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}
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#ifdef I586_CPU
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static long long cycles_per_sec = 0;
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/*
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* Figure out how fast the cyclecounter runs. This must be run with
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* clock interrupts disabled, but with the timer/counter programmed
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* and running.
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*/
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void
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calibrate_cyclecounter(void)
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{
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volatile long edx, eax, lasteax, lastedx;
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__asm __volatile(".byte 0x0f, 0x31" : "=a"(lasteax), "=d"(lastedx) : );
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DELAY(1000000);
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__asm __volatile(".byte 0x0f, 0x31" : "=a"(eax), "=d"(edx) : );
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/*
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* This assumes that you will never have a clock rate higher
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* than 4GHz, probably a good assumption.
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*/
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cycles_per_sec = (long long)edx + eax;
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cycles_per_sec -= (long long)lastedx + lasteax;
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pentium_mhz = ((long)cycles_per_sec + 500000) / 1000000; /* round up */
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}
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#endif
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/*
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* Wait "n" microseconds.
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* Relies on timer 1 counting down from (TIMER_FREQ / hz)
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* Note: timer had better have been programmed before this is first used!
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*/
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void
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DELAY(int n)
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{
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int prev_tick, tick, ticks_left, sec, usec;
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#ifdef DELAYDEBUG
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int getit_calls = 1;
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int n1;
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static int state = 0;
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if (state == 0) {
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state = 1;
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for (n1 = 1; n1 <= 10000000; n1 *= 10)
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DELAY(n1);
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state = 2;
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}
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if (state == 1)
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printf("DELAY(%d)...", n);
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#endif
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/*
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* Read the counter first, so that the rest of the setup overhead is
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* counted. Guess the initial overhead is 20 usec (on most systems it
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* takes about 1.5 usec for each of the i/o's in getit(). The loop
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* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
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* multiplications and divisions to scale the count take a while).
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*/
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prev_tick = getit(0, 0);
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n -= 20;
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/*
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* Calculate (n * (TIMER_FREQ / 1e6)) without using floating point
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* and without any avoidable overflows.
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*/
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sec = n / 1000000;
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usec = n - sec * 1000000;
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ticks_left = sec * TIMER_FREQ
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+ usec * (TIMER_FREQ / 1000000)
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+ usec * ((TIMER_FREQ % 1000000) / 1000) / 1000
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+ usec * (TIMER_FREQ % 1000) / 1000000;
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while (ticks_left > 0) {
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tick = getit(0, 0);
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#ifdef DELAYDEBUG
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++getit_calls;
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#endif
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if (tick > prev_tick)
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ticks_left -= prev_tick - (tick - timer0_divisor);
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else
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ticks_left -= prev_tick - tick;
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prev_tick = tick;
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}
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#ifdef DELAYDEBUG
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if (state == 1)
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printf(" %d calls to getit() at %d usec each\n",
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getit_calls, (n + 5) / getit_calls);
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#endif
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}
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static void
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sysbeepstop(void *chan)
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{
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outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
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release_timer2();
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beeping = 0;
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}
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int
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sysbeep(int pitch, int period)
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{
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if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
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return -1;
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disable_intr();
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outb(TIMER_CNTR2, pitch);
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outb(TIMER_CNTR2, (pitch>>8));
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enable_intr();
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if (!beeping) {
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outb(IO_PPI, inb(IO_PPI) | 3); /* enable counter2 output to speaker */
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beeping = period;
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timeout(sysbeepstop, (void *)NULL, period);
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}
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return 0;
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}
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/*
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* RTC support routines
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*/
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static int
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bcd2int(int bcd)
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{
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return(bcd/16 * 10 + bcd%16);
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}
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static int
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int2bcd(int dez)
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{
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return(dez/10 * 16 + dez%10);
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}
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static void
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writertc(int port, int val)
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{
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outb(IO_RTC, port);
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outb(IO_RTC+1, val);
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}
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static int
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readrtc(int port)
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{
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return(bcd2int(rtcin(port)));
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}
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void
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startrtclock()
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{
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int s;
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/* initialize 8253 clock */
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outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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/* Correct rounding will buy us a better precision in timekeeping */
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outb (IO_TIMER1, TIMER_DIV(hz)%256);
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outb (IO_TIMER1, TIMER_DIV(hz)/256);
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timer0_divisor = hardclock_divisor = TIMER_DIV(hz);
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/* initialize brain-dead battery powered clock */
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outb (IO_RTC, RTC_STATUSA);
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outb (IO_RTC+1, rtc_statusa);
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outb (IO_RTC, RTC_STATUSB);
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outb (IO_RTC+1, RTCSB_24HR);
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outb (IO_RTC, RTC_DIAG);
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if (s = inb (IO_RTC+1))
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printf("RTC BIOS diagnostic error %b\n", s, RTCDG_BITS);
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writertc(RTC_DIAG, 0);
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}
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/*
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* Initialize the time of day register, based on the time base which is, e.g.
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* from a filesystem.
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*/
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void
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inittodr(time_t base)
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{
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unsigned long sec, days;
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int yd;
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int year, month;
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int y, m, s;
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s = splclock();
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time.tv_sec = base;
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time.tv_usec = 0;
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splx(s);
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/* Look if we have a RTC present and the time is valid */
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if (rtcin(RTC_STATUSD) != RTCSD_PWR)
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goto wrong_time;
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|
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/* wait for time update to complete */
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/* If RTCSA_TUP is zero, we have at least 244us before next update */
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while (rtcin(RTC_STATUSA) & RTCSA_TUP);
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days = 0;
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#ifdef USE_RTC_CENTURY
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year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
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#else
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year = readrtc(RTC_YEAR) + 1900;
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if (year < 1970)
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year += 100;
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#endif
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if (year < 1970)
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goto wrong_time;
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month = readrtc(RTC_MONTH);
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for (m = 1; m < month; m++)
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days += daysinmonth[m-1];
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if ((month > 2) && LEAPYEAR(year))
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days ++;
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days += readrtc(RTC_DAY) - 1;
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yd = days;
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for (y = 1970; y < year; y++)
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days += DAYSPERYEAR + LEAPYEAR(y);
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sec = ((( days * 24 +
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readrtc(RTC_HRS)) * 60 +
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readrtc(RTC_MIN)) * 60 +
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readrtc(RTC_SEC));
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/* sec now contains the number of seconds, since Jan 1 1970,
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in the local time zone */
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|
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sec += tz.tz_minuteswest * 60;
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|
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s = splclock();
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time.tv_sec = sec;
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splx(s);
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return;
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|
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wrong_time:
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printf("Invalid time in real time clock.\n");
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printf("Check and reset the date immediately!\n");
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}
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|
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/*
|
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* Write system time back to RTC
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*/
|
|
void resettodr()
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|
{
|
|
unsigned long tm;
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int y, m, fd, r, s;
|
|
|
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if (disable_rtc_set)
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return;
|
|
|
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s = splclock();
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tm = time.tv_sec;
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splx(s);
|
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|
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/* First, disable clock updates */
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writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
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|
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/* Calculate local time to put in RTC */
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tm -= tz.tz_minuteswest * 60 + adjkerntz;
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writertc(RTC_SEC, int2bcd(tm%60)); tm /= 60; /* Write back Seconds */
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writertc(RTC_MIN, int2bcd(tm%60)); tm /= 60; /* Write back Minutes */
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writertc(RTC_HRS, int2bcd(tm%24)); tm /= 24; /* Write back Hours */
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/* We have now the days since 01-01-1970 in tm */
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writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
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for (y=1970;; y++)
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if ((tm - DAYSPERYEAR - LEAPYEAR(y)) > tm)
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break;
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else
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tm -= DAYSPERYEAR + LEAPYEAR(y);
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|
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/* Now we have the years in y and the day-of-the-year in tm */
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writertc(RTC_YEAR, int2bcd(y%100)); /* Write back Year */
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#ifdef USE_RTC_CENTURY
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writertc(RTC_CENTURY, int2bcd(y/100)); /* ... and Century */
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|
#endif
|
|
if (LEAPYEAR(y) && (tm >= 31+29))
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tm--; /* Subtract Feb-29 */
|
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for (m=1;; m++)
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if (tm - daysinmonth[m-1] > tm)
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break;
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else
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tm -= daysinmonth[m-1];
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writertc(RTC_MONTH, int2bcd(m)); /* Write back Month */
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writertc(RTC_DAY, int2bcd(tm+1)); /* Write back Day */
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|
|
/* enable time updates */
|
|
writertc(RTC_STATUSB, RTCSB_PINTR | RTCSB_24HR);
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}
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|
|
#ifdef garbage
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/*
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* Initialze the time of day register, based on the time base which is, e.g.
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* from a filesystem.
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*/
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test_inittodr(time_t base)
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{
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outb(IO_RTC,9); /* year */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,8); /* month */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,7); /* day */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,4); /* hour */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,2); /* minutes */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,0); /* seconds */
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printf("%d\n",bcd(inb(IO_RTC+1)));
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time.tv_sec = base;
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}
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#endif
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/*
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* Wire clock interrupt in.
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*/
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static u_int clkmask = HWI_MASK | SWI_MASK;
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static u_int rtcmask = SWI_CLOCK_MASK;
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void
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enablertclock()
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{
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, clkintr,
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&clkmask, /* unit */ 0);
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INTREN(IRQ0);
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register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, rtcintr,
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&rtcmask, /* unit */ 0);
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INTREN(IRQ8);
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outb(IO_RTC, RTC_STATUSB);
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outb(IO_RTC+1, RTCSB_PINTR | RTCSB_24HR);
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}
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void
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cpu_initclocks()
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{
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stathz = RTC_NOPROFRATE;
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profhz = RTC_PROFRATE;
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enablertclock();
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}
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void
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setstatclockrate(int newhz)
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{
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if(newhz == RTC_PROFRATE) {
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rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
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} else {
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rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
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}
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outb(IO_RTC, RTC_STATUSA);
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outb(IO_RTC+1, rtc_statusa);
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}
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