31bf2875ea
Different revisions support different operations. Refer to Intel External Design Specifications to figure out what your hardware supports. Sponsored by: EMC / Isilon Storage Division
248 lines
7.3 KiB
Groff
248 lines
7.3 KiB
Groff
.\" Copyright (c) 2015 EMC / Isilon Storage Division
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd December 17, 2015
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.Dt IOAT 4
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.Os
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.Sh NAME
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.Nm I/OAT
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.Nd Intel I/O Acceleration Technology
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.Sh SYNOPSIS
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To compile this driver into your kernel,
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place the following line in your kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device ioat"
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.Ed
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.Pp
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Or, to load the driver as a module at boot, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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ioat_load="YES"
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.Ed
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.Pp
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In
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.Xr loader.conf 5 :
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.Pp
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.Cd hw.ioat.force_legacy_interrupts=0
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.Pp
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In
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.Xr loader.conf 5 or
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.Xr sysctl.conf 5 :
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.Pp
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.Cd hw.ioat.enable_ioat_test=0
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.Cd hw.ioat.debug_level=0
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(only critical errors; maximum of 3)
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.Pp
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.Ft typedef void
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.Fn (*bus_dmaengine_callback_t) "void *arg" "int error"
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.Pp
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.Ft bus_dmaengine_t
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.Fn ioat_get_dmaengine "uint32_t channel_index"
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.Ft void
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.Fn ioat_put_dmaengine "bus_dmaengine_t dmaengine"
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.Ft int
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.Fn ioat_get_hwversion "bus_dmaengine_t dmaengine"
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.Ft int
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.Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay"
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.Ft uint16_t
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.Fn ioat_get_max_coalesce_period "bus_dmaengine_t dmaengine"
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.Ft void
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.Fn ioat_acquire "bus_dmaengine_t dmaengine"
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.Ft void
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.Fn ioat_release "bus_dmaengine_t dmaengine"
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.Ft struct bus_dmadesc *
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.Fo ioat_copy
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_addr_t dst"
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.Fa "bus_addr_t src"
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.Fa "bus_size_t len"
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.Fa "bus_dmaengine_callback_t callback_fn"
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.Fa "void *callback_arg"
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.Fa "uint32_t flags"
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.Fc
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.Ft struct bus_dmadesc *
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.Fo ioat_copy_8k_aligned
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_addr_t dst1"
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.Fa "bus_addr_t dst2"
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.Fa "bus_addr_t src1"
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.Fa "bus_addr_t src2"
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.Fa "bus_dmaengine_callback_t callback_fn"
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.Fa "void *callback_arg"
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.Fa "uint32_t flags"
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.Fc
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.Ft struct bus_dmadesc *
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.Fo ioat_blockfill
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_addr_t dst"
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.Fa "uint64_t fillpattern"
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.Fa "bus_size_t len"
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.Fa "bus_dmaengine_callback_t callback_fn"
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.Fa "void *callback_arg"
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.Fa "uint32_t flags"
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.Fc
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.Ft struct bus_dmadesc *
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.Fo ioat_null
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.Fa "bus_dmaengine_t dmaengine"
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.Fa "bus_dmaengine_callback_t callback_fn"
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.Fa "void *callback_arg"
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.Fa "uint32_t flags"
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.Fc
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.Sh DESCRIPTION
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The
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.Nm
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driver provides a kernel API to a variety of DMA engines on some Intel server
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platforms.
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.Pp
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There is a number of DMA channels per CPU package.
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(Typically 4 or 8.)
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Each may be used independently.
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Operations on a single channel proceed sequentially.
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.Pp
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Blockfill operations can be used to write a 64-bit pattern to memory.
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.Pp
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Copy operations can be used to offload memory copies to the DMA engines.
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.Pp
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Null operations do nothing, but may be used to test the interrupt and callback
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mechanism.
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.Pp
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All operations can optionally trigger an interrupt at completion with the
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.Ar DMA_EN_INT
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flag.
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For example, a user might submit multiple operations to the same channel and
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only enable an interrupt and callback for the last operation.
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.Pp
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The hardware can delay and coalesce interrupts on a given channel for a
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configurable period of time, in microseconds.
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This may be desired to reduce the processing and interrupt overhead per
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descriptor, especially for workflows consisting of many small operations.
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Software can control this on a per-channel basis with the
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.Fn ioat_set_interrupt_coalesce
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API.
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The
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.Fn ioat_get_max_coalesce_period
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API can be used to determine the maximum coalescing period supported by the
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hardware, in microseconds.
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Current platforms support up to a 16.383 millisecond coalescing period.
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Optimal configuration will vary by workflow and desired operation latency.
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.Pp
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All operations are safe to use in a non-blocking context with the
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.Ar DMA_NO_WAIT
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flag.
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(Of course, allocations may fail and operations requested with
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.Ar DMA_NO_WAIT
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may return NULL.)
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.Pp
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All operations, as well as
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.Fn ioat_get_dmaengine ,
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can return NULL in special circumstances.
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For example, if the
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.Nm
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driver is being unloaded, or the administrator has induced a hardware reset, or
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a usage error has resulted in a hardware error state that needs to be recovered
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from.
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.Pp
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It is invalid to attempt to submit new DMA operations in a
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.Fa bus_dmaengine_callback_t
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context.
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.Sh USAGE
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A typical user will lookup the DMA engine object for a given channel with
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.Fn ioat_get_dmaengine .
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When the user wants to offload a copy, they will first
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.Fn ioat_acquire
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the
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.Ar bus_dmaengine_t
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object for exclusive access to enqueue operations on that channel.
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Then, they will submit one or more operations using
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.Fn ioat_blockfill ,
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.Fn ioat_copy ,
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or
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.Fn ioat_null .
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After queuing one or more individual DMA operations, they will
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.Fn ioat_release
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the
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.Ar bus_dmaengine_t
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to drop their exclusive access to the channel.
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The routine they provided for the
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.Fa callback_fn
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argument will be invoked with the provided
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.Fa callback_arg
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when the operation is complete.
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When they are finished with the
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.Ar bus_dmaengine_t ,
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the user should
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.Fn ioat_put_dmaengine .
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.Pp
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Users MUST NOT block between
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.Fn ioat_acquire
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and
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.Fn ioat_release .
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Users SHOULD NOT hold
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.Ar bus_dmaengine_t
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references for a very long time to enable fault recovery and kernel module
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unload.
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.Pp
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For an example of usage, see
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.Pa src/sys/dev/ioat/ioat_test.c .
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.Sh FILES
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.Bl -tag
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.It Pa /dev/ioat_test
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test device for
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.Xr ioatcontrol 8
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.El
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.Sh SEE ALSO
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.Xr ioatcontrol 8
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.Sh HISTORY
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The
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.Nm
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driver first appeared in
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.Fx 11.0 .
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.Sh AUTHORS
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The
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.Nm
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driver was developed by
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.An \&Jim Harris Aq Mt jimharris@FreeBSD.org ,
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.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com ,
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and
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.An \&Conrad Meyer Aq Mt cem@FreeBSD.org .
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This manual page was written by
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.An \&Conrad Meyer Aq Mt cem@FreeBSD.org .
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.Sh CAVEATS
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Copy operation takes bus addresses as parameters, not virtual addresses.
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.Pp
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Buffers for individual copy operations must be physically contiguous.
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.Pp
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Copies larger than max transfer size (1MB, but may vary by hardware) are not
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supported.
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Future versions will likely support this by breaking up the transfer into
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smaller sizes.
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.Sh BUGS
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The
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.Nm
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driver only supports blockfill, copy, and null operations at this time.
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The driver does not yet support advanced DMA modes, such as XOR, that some
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I/OAT devices support.
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