292 lines
14 KiB
C
292 lines
14 KiB
C
/*
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* Copyright (c) 1998, 1999 Eduardo E. Horvath
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* Copyright (c) 1999 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _SPARC64_PCI_PSYCHOREG_H_
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#define _SPARC64_PCI_PSYCHOREG_H_
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/*
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* Sun4u PCI definitions. Here's where we deal w/the machine
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* dependencies of psycho and the PCI controller on the UltraIIi.
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*
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* All PCI registers are bit-swapped, however they are not byte-swapped.
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* This means that they must be accessed using little-endian access modes,
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* either map the pages little-endian or use little-endian ASIs.
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*
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* PSYCHO implements two PCI buses, A and B.
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*/
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/*
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* psycho register offset.s
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*
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* NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000
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* respectively.
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*/
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#define PSR_UPA_PORTID 0x0000 /* UPA port ID register */
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#define PSR_UPA_CONFIG 0x0008 /* UPA config register */
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#define PSR_CS 0x0010 /* PSYCHO control/status register */
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#define PSR_ECCC 0x0020 /* ECC control register */
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#define PSR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */
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#define PSR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */
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#define PSR_CE_AFS 0x0040 /* Correctable Error AFSR */
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#define PSR_CE_AFA 0x0048 /* Correctable Error AFAR */
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#define PSR_PM_CTL 0x0100 /* Performance monitor control reg */
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#define PSR_PM_COUNT 0x0108 /* Performance monitor counter reg */
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#define PSR_IOMMU 0x0200 /* IOMMU registers. */
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#define PSR_PCIA0_INT_MAP 0x0c00 /* PCI bus a slot 0 irq map reg */
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#define PSR_PCIA1_INT_MAP 0x0c08 /* PCI bus a slot 1 irq map reg */
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#define PSR_PCIA2_INT_MAP 0x0c10 /* PCI bus a slot 2 irq map reg (IIi) */
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#define PSR_PCIA3_INT_MAP 0x0c18 /* PCI bus a slot 3 irq map reg (IIi) */
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#define PSR_PCIB0_INT_MAP 0x0c20 /* PCI bus b slot 0 irq map reg */
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#define PSR_PCIB1_INT_MAP 0x0c28 /* PCI bus b slot 1 irq map reg */
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#define PSR_PCIB2_INT_MAP 0x0c30 /* PCI bus b slot 2 irq map reg */
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#define PSR_PCIB3_INT_MAP 0x0c38 /* PCI bus b slot 3 irq map reg */
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#define PSR_SCSI_INT_MAP 0x1000 /* SCSI interrupt map reg */
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#define PSR_ETHER_INT_MAP 0x1008 /* ethernet interrupt map reg */
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#define PSR_BPP_INT_MAP 0x1010 /* parallel interrupt map reg */
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#define PSR_AUDIOR_INT_MAP 0x1018 /* audio record interrupt map reg */
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#define PSR_AUDIOP_INT_MAP 0x1020 /* audio playback interrupt map reg */
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#define PSR_POWER_INT_MAP 0x1028 /* power fail interrupt map reg */
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#define PSR_SKBDMS_INT_MAP 0x1030 /* serial/kbd/mouse interrupt map reg */
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#define PSR_FD_INT_MAP 0x1038 /* floppy interrupt map reg */
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#define PSR_SPARE_INT_MAP 0x1040 /* spare interrupt map reg */
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#define PSR_KBD_INT_MAP 0x1048 /* kbd [unused] interrupt map reg */
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#define PSR_MOUSE_INT_MAP 0x1050 /* mouse [unused] interrupt map reg */
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#define PSR_SERIAL_INT_MAP 0x1058 /* second serial interrupt map reg */
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#define PSR_TIMER0_INT_MAP 0x1060 /* timer 0 interrupt map reg */
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#define PSR_TIMER1_INT_MAP 0x1068 /* timer 1 interrupt map reg */
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#define PSR_UE_INT_MAP 0x1070 /* UE interrupt map reg */
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#define PSR_CE_INT_MAP 0x1078 /* CE interrupt map reg */
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#define PSR_PCIAERR_INT_MAP 0x1080 /* PCI bus a error interrupt map reg */
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#define PSR_PCIBERR_INT_MAP 0x1088 /* PCI bus b error interrupt map reg */
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#define PSR_PWRMGT_INT_MAP 0x1090 /* power mgmt wake interrupt map reg */
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#define PSR_FFB0_INT_MAP 0x1098 /* FFB0 graphics interrupt map reg */
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#define PSR_FFB1_INT_MAP 0x10a0 /* FFB1 graphics interrupt map reg */
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/* Note: clear interrupt 0 registers are not really used */
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#define PSR_PCIA0_INT_CLR 0x1400 /* PCI a slot 0 clear int regs 0..3 */
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#define PSR_PCIA1_INT_CLR 0x1420 /* PCI a slot 1 clear int regs 0..3 */
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#define PSR_PCIA2_INT_CLR 0x1440 /* PCI a slot 1 clear int regs 0..3 */
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#define PSR_PCIA3_INT_CLR 0x1460 /* PCI a slot 1 clear int regs 0..3 */
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#define PSR_PCIB0_INT_CLR 0x1480 /* PCI b slot 0 clear int regs 0..3 */
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#define PSR_PCIB1_INT_CLR 0x14a0 /* PCI b slot 1 clear int regs 0..3 */
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#define PSR_PCIB2_INT_CLR 0x14c0 /* PCI b slot 2 clear int regs 0..3 */
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#define PSR_PCIB3_INT_CLR 0x14d0 /* PCI b slot 3 clear int regs 0..3 */
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#define PSR_SCSI_INT_CLR 0x1800 /* SCSI clear int reg */
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#define PSR_ETHER_INT_CLR 0x1808 /* ethernet clear int reg */
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#define PSR_BPP_INT_CLR 0x1810 /* parallel clear int reg */
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#define PSR_AUDIOR_INT_CLR 0x1818 /* audio record clear int reg */
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#define PSR_AUDIOP_INT_CLR 0x1820 /* audio playback clear int reg */
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#define PSR_POWER_INT_CLR 0x1828 /* power fail clear int reg */
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#define PSR_SKBDMS_INT_CLR 0x1830 /* serial/kbd/mouse clear int reg */
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#define PSR_FD_INT_CLR 0x1838 /* floppy clear int reg */
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#define PSR_SPARE_INT_CLR 0x1840 /* spare clear int reg */
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#define PSR_KBD_INT_CLR 0x1848 /* kbd [unused] clear int reg */
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#define PSR_MOUSE_INT_CLR 0x1850 /* mouse [unused] clear int reg */
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#define PSR_SERIAL_INT_CLR 0x1858 /* second serial clear int reg */
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#define PSR_TIMER0_INT_CLR 0x1860 /* timer 0 clear int reg */
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#define PSR_TIMER1_INT_CLR 0x1868 /* timer 1 clear int reg */
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#define PSR_UE_INT_CLR 0x1870 /* UE clear int reg */
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#define PSR_CE_INT_CLR 0x1878 /* CE clear int reg */
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#define PSR_PCIAERR_INT_CLR 0x1880 /* PCI bus a error clear int reg */
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#define PSR_PCIBERR_INT_CLR 0x1888 /* PCI bus b error clear int reg */
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#define PSR_PWRMGT_INT_CLR 0x1890 /* power mgmt wake clr interrupt reg */
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#define PSR_INTR_RETRY_TIM 0x1a00 /* interrupt retry timer */
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#define PSR_TC0 0x1c00 /* timer/counter 0 */
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#define PSR_TC1 0x1c10 /* timer/counter 1 */
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#define PSR_DMA_WRITE_SYNC 0x1c20 /* PCI DMA write sync register (IIi) */
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#define PSR_PCICTL0 0x2000 /* PCICTL registers for 1st psycho. */
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#define PSR_PCICTL1 0x4000 /* PCICTL registers for 2nd psycho. */
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#define PSR_DMA_SCB_DIAG0 0xa000 /* DMA scoreboard diag reg 0 */
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#define PSR_DMA_SCB_DIAG1 0xa008 /* DMA scoreboard diag reg 1 */
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#define PSR_IOMMU_SVADIAG 0xa400 /* IOMMU virtual addr diag reg */
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#define PSR_IOMMU_TLB_CMP_DIAG 0xa408 /* IOMMU TLB tag compare diag reg */
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#define PSR_IOMMU_QUEUE_DIAG 0xa500 /* IOMMU LRU queue diag regs 0..15 */
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#define PSR_IOMMU_TLB_TAG_DIAG 0xa580 /* TLB tag diag regs 0..15 */
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#define PSR_IOMMU_TLB_DATA_DIAG 0xa600 /* TLB data RAM diag regs 0..15 */
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#define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */
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#define PSR_OBIO_INT_DIAG 0xa808 /* OBIO and misc int state diag reg */
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#define PSR_STRBUF_DIAG 0xb000 /* Streaming buffer diag regs */
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/*
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* Here is the rest of the map, which we're not specifying:
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*
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* 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
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* 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header
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* 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header
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* 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space
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* 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space
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* 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space
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* 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space
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*
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* NB: config and I/O space can use 1-4 byte accesses, not 8 byte
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* accesses. Memory space can use any sized accesses.
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*
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* Note that the SUNW,sabre/SUNW,simba combinations found on the
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* Ultra5 and Ultra10 machines uses slightly differrent addresses
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* than the above. This is mostly due to the fact that the APB is
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* a multi-function PCI device with two PCI bridges, and the U2P is
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* two separate PCI bridges. It uses the same PCI configuration
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* space, though the configuration header for each PCI bus is
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* located differently due to the SUNW,simba PCI busses being
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* function 0 and function 1 of the APB, whereas the psycho's are
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* each their own PCI device. The I/O and memory spaces are each
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* split into 8 equally sized areas (8x2MB blocks for I/O space,
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* and 8x512MB blocks for memory space). These are allocated in to
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* either PCI A or PCI B, or neither in the APB's `I/O Address Map
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* Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf)
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* registers of each simba. We must ensure that both of the
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* following are correct (the prom should do this for us):
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*
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* (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
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*
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* (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
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*
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* 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
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* 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header
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* 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header
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* 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided)
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* 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided)
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*/
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/*
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* PSR_CS defines:
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*
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* 63 59 55 50 45 4 3 2 1 0
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* +------+------+------+------+--//---+--------+-------+-----+------+
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* | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE |
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* +------+------+------+------+--//---+--------+-------+-----+------+
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*
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*/
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#define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf))
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#define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf))
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#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f))
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#define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f))
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#define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */
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#define PSYCHO_CSR_APERR 4 /* UPA addr parity error */
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#define PSYCHO_CSR_IAP 2 /* invert UPA address parity */
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#define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */
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/* Offsets into the PSR_PCICTL* register block. */
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#define PCR_CS 0x0000 /* PCI control/status register */
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#define PCR_AFS 0x0010 /* PCI AFSR register */
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#define PCR_AFA 0x0018 /* PCI AFAR register */
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#define PCR_DIAG 0x0020 /* PCI diagnostic register */
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#define PCR_TAS 0x0028 /* PCI target address space reg (IIi) */
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#define PCR_STRBUF 0x0800 /* IOMMU streaming buffer registers. */
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/* Device space defines. */
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#define PSYCHO_CONF_SIZE 0x1000000
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#define PSYCHO_CONF_BUS_SHIFT 16
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#define PSYCHO_CONF_DEV_SHIFT 11
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#define PSYCHO_CONF_FUNC_SHIFT 8
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#define PSYCHO_CONF_REG_SHIFT 0
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#define PSYCHO_IO_SIZE 0x1000000
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#define PSYCHO_MEM_SIZE 0x100000000
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#define PSYCHO_CONF_OFF(bus, slot, func, reg) \
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(((bus) << PSYCHO_CONF_BUS_SHIFT) | \
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((slot) << PSYCHO_CONF_DEV_SHIFT) | \
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((func) << PSYCHO_CONF_FUNC_SHIFT) | \
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((reg) << PSYCHO_CONF_REG_SHIFT))
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/* what the bits mean! */
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/* PCI [a|b] control/status register */
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/* note that the sabre only has one set of PCI control/status registers */
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#define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */
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#define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */
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#define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
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#define PCICTL_CPU_PRIO 0x0000000000100000 /* PCI arbitration parking */
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#define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI arbitration parking */
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#define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */
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#define PCICTL_RTRYWAIT 0x0000000000000080 /* PCI error interrupt enable */
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#define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */
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#define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */
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/* Uncorrectable error asynchronous fault status registers */
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#define UEAFSR_BLK (1UL << 22) /* pri. error caused by read */
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#define UEAFSR_P_DTE (1UL << 56) /* pri. DMA translation error */
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#define UEAFSR_S_DTE (1UL << 57) /* sec. DMA translation error */
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#define UEAFSR_S_DWR (1UL << 58) /* sec. error during write */
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#define UEAFSR_S_DRD (1UL << 59) /* sec. error during read */
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#define UEAFSR_P_DWR (1UL << 61) /* pri. error during write */
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#define UEAFSR_P_DRD (1UL << 62) /* pri. error during read */
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/*
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* these are the PROM structures we grovel
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*/
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/*
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* For the physical adddresses split into 3 32 bit values, we deocde
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* them like the following (IEEE1275 PCI Bus binding 2.0, 2.2.1.1
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* Numerical Representation):
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*
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* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
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* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* phys.lo cell: llllllll llllllll llllllll llllllll
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*
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* where these bits affect the address' properties:
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* n not-relocatable
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* p prefetchable
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* t aliased (non-relocatable IO), below 1MB (memory) or
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* below 64KB (reloc. IO)
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* ss address space code:
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* 00 - configuration space
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* 01 - I/O space
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* 10 - 32 bit memory space
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* 11 - 64 bit memory space
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* bb..bb 8 bit bus number
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* ddddd 5 bit device number
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* fff 3 bit function number
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* rr..rr 8 bit register number
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* hh..hh 32 bit unsigned value
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* ll..ll 32 bit unsigned value
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* the values of hh..hh and ll..ll are combined to form a larger number.
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*
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* For config space, we don't have to do much special. For I/O space,
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* hh..hh must be zero, and if n == 0 ll..ll is the offset from the
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* start of I/O space, otherwise ll..ll is the I/O space. For memory
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* space, hh..hh must be zero for the 32 bit space, and is the high 32
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* bits in 64 bit space, with ll..ll being the low 32 bits in both cases,
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* with offset handling being driver via `n == 0' as for I/O space.
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*/
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/* commonly used */
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#define TAG2BUS(tag) ((tag) >> 16) & 0xff;
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#define TAG2DEV(tag) ((tag) >> 11) & 0x1f;
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#define TAG2FN(tag) ((tag) >> 8) & 0x7;
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#define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */
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#define INTPCIOBINOX(x) ((x) & 0x1f) /* OBIO ino index (for PCI machines) */
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#define INTPCIINOX(x) (((x) & 0x1c) >> 2) /* PCI ino index */
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#endif /* _SPARC64_PCI_PSYCHOREG_H_ */
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