7f725bcd5c
The NAND Flash environment consists of several distinct components: - NAND framework (drivers harness for NAND controllers and NAND chips) - NAND simulator (NANDsim) - NAND file system (NAND FS) - Companion tools and utilities - Documentation (manual pages) This work is still experimental. Please use with caution. Obtained from: Semihalf Supported by: FreeBSD Foundation, Juniper Networks
176 lines
4.7 KiB
C
176 lines
4.7 KiB
C
/*-
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* Copyright (C) 2009-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _NANDSIM_H_
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#define _NANDSIM_H_
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#include <sys/ioccom.h>
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#include <sys/types.h>
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#define MAX_SIM_DEV 4
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#define MAX_CTRL_CS 4
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#define MAX_ECC_BYTES 512
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#define MAX_BAD_BLOCKS 512
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#define DEV_MODEL_STR_SIZE 21
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#define MAN_STR_SIZE 13
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#define FILENAME_SIZE 20
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#define MAX_CHIPS (MAX_SIM_DEV*MAX_CTRL_CS)
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#define NANDSIM_OUTPUT_NONE 0x0
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#define NANDSIM_OUTPUT_CONSOLE 0x1
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#define NANDSIM_OUTPUT_RAM 0x2
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#define NANDSIM_OUTPUT_FILE 0x3
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struct sim_ctrl_chip {
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uint8_t ctrl_num;
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uint8_t chip_num;
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};
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#define NANDSIM_BASE 'A'
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struct sim_param {
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uint8_t log_level;
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uint8_t log_output;
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};
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#define NANDSIM_SIM_PARAM _IOW(NANDSIM_BASE, 1, struct sim_param)
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struct sim_ctrl {
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uint8_t running;
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uint8_t created;
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uint8_t num;
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uint8_t num_cs;
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uint8_t ecc;
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char filename[FILENAME_SIZE];
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uint16_t ecc_layout[MAX_ECC_BYTES];
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};
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#define NANDSIM_CREATE_CTRL _IOW(NANDSIM_BASE, 2, struct sim_ctrl)
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#define NANDSIM_DESTROY_CTRL _IOW(NANDSIM_BASE, 3, int)
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struct sim_chip {
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uint8_t num;
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uint8_t ctrl_num;
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uint8_t created;
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uint8_t device_id;
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uint8_t manufact_id;
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char device_model[DEV_MODEL_STR_SIZE];
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char manufacturer[MAN_STR_SIZE];
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uint8_t col_addr_cycles;
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uint8_t row_addr_cycles;
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uint8_t features;
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uint8_t width;
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uint32_t page_size;
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uint32_t oob_size;
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uint32_t pgs_per_blk;
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uint32_t blks_per_lun;
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uint32_t luns;
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uint32_t prog_time;
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uint32_t erase_time;
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uint32_t read_time;
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uint32_t ccs_time;
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uint32_t error_ratio;
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uint32_t wear_level;
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uint32_t bad_block_map[MAX_BAD_BLOCKS];
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uint8_t is_wp;
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};
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#define NANDSIM_CREATE_CHIP _IOW(NANDSIM_BASE, 3, struct sim_chip)
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struct sim_chip_destroy {
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uint8_t ctrl_num;
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uint8_t chip_num;
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};
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#define NANDSIM_DESTROY_CHIP _IOW(NANDSIM_BASE, 4, struct sim_chip_destroy)
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#define NANDSIM_START_CTRL _IOW(NANDSIM_BASE, 5, int)
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#define NANDSIM_STOP_CTRL _IOW(NANDSIM_BASE, 6, int)
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#define NANDSIM_RESTART_CTRL _IOW(NANDSIM_BASE, 7, int)
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#define NANDSIM_STATUS_CTRL _IOWR(NANDSIM_BASE, 8, struct sim_ctrl)
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#define NANDSIM_STATUS_CHIP _IOWR(NANDSIM_BASE, 9, struct sim_chip)
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struct sim_mod {
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uint8_t chip_num;
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uint8_t ctrl_num;
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uint32_t field;
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uint32_t new_value;
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};
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#define SIM_MOD_LOG_LEVEL 0
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#define SIM_MOD_ERASE_TIME 1
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#define SIM_MOD_PROG_TIME 2
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#define SIM_MOD_READ_TIME 3
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#define SIM_MOD_CCS_TIME 4
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#define SIM_MOD_ERROR_RATIO 5
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#define NANDSIM_MODIFY _IOW(NANDSIM_BASE, 10, struct sim_mod)
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#define NANDSIM_FREEZE _IOW(NANDSIM_BASE, 11, struct sim_ctrl_chip)
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struct sim_error {
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uint8_t ctrl_num;
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uint8_t chip_num;
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uint32_t page_num;
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uint32_t column;
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uint32_t len;
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uint32_t pattern;
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};
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#define NANDSIM_INJECT_ERROR _IOW(NANDSIM_BASE, 20, struct sim_error)
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#define NANDSIM_GOOD_BLOCK 0
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#define NANDSIM_BAD_BLOCK 1
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struct sim_block_state {
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uint8_t ctrl_num;
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uint8_t chip_num;
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uint32_t block_num;
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int wearout;
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uint8_t state;
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};
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#define NANDSIM_SET_BLOCK_STATE _IOW(NANDSIM_BASE, 21, struct sim_block_state)
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#define NANDSIM_GET_BLOCK_STATE _IOWR(NANDSIM_BASE, 22, struct sim_block_state)
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struct sim_log {
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uint8_t ctrl_num;
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char* log;
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size_t len;
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};
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#define NANDSIM_PRINT_LOG _IOWR(NANDSIM_BASE, 23, struct sim_log)
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struct sim_dump {
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uint8_t ctrl_num;
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uint8_t chip_num;
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uint32_t block_num;
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uint32_t len;
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void* data;
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};
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#define NANDSIM_DUMP _IOWR(NANDSIM_BASE, 24, struct sim_dump)
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#define NANDSIM_RESTORE _IOWR(NANDSIM_BASE, 25, struct sim_dump)
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#endif /* _NANDSIM_H_ */
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