bc0ad9a99d
The MEM_UOPS_RETIRED actually work the same way as the Sandy Bridge counters, but the counters were documented in a different way and that seemed to cause the Ivy Bridge counters to be implemented incorrectly. Use the same counter definitions as Sandy Bridge. While I'm here, rename the counters to match what's documented in the datasheet. Differential Revision: https://reviews.freebsd.org/D1590 MFC after: 1 month Sponsored by: Sandvine Inc.
884 lines
31 KiB
Groff
884 lines
31 KiB
Groff
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd Jan 25, 2013
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.Dt PMC.IVYBRIDGEXEON 3
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.Os
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.Sh NAME
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.Nm pmc.ivybridgexeon
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.Nd measurement events for
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.Tn Intel
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.Tn Ivy Bridge Xeon
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Ivy Bridge Xeon"
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CPUs contain PMCs conforming to version 2 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs may contain up to three classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_IAP"
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.It Li PMC_CLASS_IAF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_IAP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Ivy Bridge Xeon PMCs are documented in
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.Rs
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.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
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.%N "Order Number: 325462-045US"
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.%D January 2013
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.%Q "Intel Corporation"
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.Re
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.Ss IVYBRIDGE FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.iaf 3 .
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.Ss IVYBRIDGE PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li rsp= Ns Ar value
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Configure the Off-core Response bits.
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.Bl -tag -width indent
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.It Li REQ_DMND_DATA_RD
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Counts the number of demand and DCU prefetch data reads of full and partial
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cachelines as well as demand data page table entry cacheline reads. Does not
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count L2 data read prefetches or instruction fetches.
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.It Li REQ_DMND_RFO
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Counts the number of demand and DCU prefetch reads for ownership (RFO)
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requests generated by a write to data cacheline. Does not count L2 RFO
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prefetches.
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.It Li REQ_DMND_IFETCH
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Counts the number of demand and DCU prefetch instruction cacheline reads.
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Does not count L2 code read prefetches.
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.It Li REQ_WB
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Counts the number of writeback (modified to exclusive) transactions.
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.It Li REQ_PF_DATA_RD
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Counts the number of data cacheline reads generated by L2 prefetchers.
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.It Li REQ_PF_RFO
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Counts the number of RFO requests generated by L2 prefetchers.
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.It Li REQ_PF_IFETCH
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Counts the number of code reads generated by L2 prefetchers.
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.It Li REQ_PF_LLC_DATA_RD
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L2 prefetcher to L3 for loads.
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.It Li REQ_PF_LLC_RFO
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RFO requests generated by L2 prefetcher
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.It Li REQ_PF_LLC_IFETCH
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L2 prefetcher to L3 for instruction fetches.
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.It Li REQ_BUS_LOCKS
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Bus lock and split lock requests.
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.It Li REQ_STRM_ST
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Streaming store requests.
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.It Li REQ_OTHER
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Any other request that crosses IDI, including I/O.
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.It Li RES_ANY
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Catch all value for any response types.
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.It Li RES_SUPPLIER_NO_SUPP
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No Supplier Information available.
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.It Li RES_SUPPLIER_LLC_HITM
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M-state initial lookup stat in L3.
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.It Li RES_SUPPLIER_LLC_HITE
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E-state.
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.It Li RES_SUPPLIER_LLC_HITS
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S-state.
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.It Li RES_SUPPLIER_LLC_HITF
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F-state.
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.It Li RES_SUPPLIER_LOCAL
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Local DRAM Controller.
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.It Li RES_SNOOP_SNP_NONE
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No details on snoop-related information.
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.It Li RES_SNOOP_SNP_NO_NEEDED
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No snoop was needed to satisfy the request.
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.It Li RES_SNOOP_SNP_MISS
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A snoop was needed and it missed all snooped caches:
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-For LLC Hit, ReslHitl was returned by all cores
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-For LLC Miss, Rspl was returned by all sockets and data was returned from
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DRAM.
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.It Li RES_SNOOP_HIT_NO_FWD
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A snoop was needed and it hits in at least one snooped cache. Hit denotes a
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cache-line was valid before snoop effect. This includes:
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-Snoop Hit w/ Invalidation (LLC Hit, RFO)
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-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
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-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
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In the LLC Miss case, data is returned from DRAM.
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.It Li RES_SNOOP_HIT_FWD
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A snoop was needed and data was forwarded from a remote socket.
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This includes:
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-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
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.It Li RES_SNOOP_HITM
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A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
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cache-line was in modified state before effect as a results of snoop. This
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includes:
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-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
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-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
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-Snoop MtoS (LLC Hit, IFetch/Data_RD).
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.It Li RES_NON_DRAM
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Target was non-DRAM system address. This includes MMIO transactions.
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.El
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.It Li os
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Configure the PMC to count events happening at processor privilege
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level 0.
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.It Li usr
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Configure the PMC to count events occurring at privilege levels 1, 2
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or 3.
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.El
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.Pp
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If neither of the
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.Dq Li os
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or
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.Dq Li usr
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qualifiers are specified, the default is to enable both.
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.Ss Event Specifiers (Programmable PMCs)
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Ivy Bridge programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li LD_BLOCKS.STORE_FORWARD
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.Pq Event 03H , Umask 02H
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loads blocked by overlapping with store buffer that cannot be forwarded .
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.It Li MISALIGN_MEM_REF.LOADS
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.Pq Event 05H , Umask 01H
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Speculative cache-line split load uops dispatched to L1D.
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.It Li MISALIGN_MEM_REF.STORES
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.Pq Event 05H , Umask 02H
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Speculative cache-line split Store- address uops dispatched to L1D.
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.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
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.Pq Event 07H , Umask 01H
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False dependencies in MOB due to partial compare on address.
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.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
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.Pq Event 08H , Umask 81H
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Misses in all TLB levels that cause a page walk of any page size from demand loads.
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.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED
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.Pq Event 08H , Umask 82H
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Misses in all TLB levels that caused page walk completed of any size by demand loads.
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.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION
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.Pq Event 08H , Umask 84H
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Cycle PMH is busy with a walk due to demand loads.
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.It Li UOPS_ISSUED.ANY
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.Pq Event 0EH , Umask 01H
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Increments each cycle the # of Uops issued by the RAT to RS.
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Set Cmask = 1, Inv = 1to count stalled cycles.
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Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
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.It Li UOPS_ISSUED.FLAGS_MERGE
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.Pq Event 0EH , Umask 10H
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Number of flags-merge uops allocated. Such uops adds delay.
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.It Li UOPS_ISSUED.SLOW_LEA
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.Pq Event 0EH , Umask 20H
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Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2
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sources + immediate) regardless if as a result of LEA instruction or not.
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.It Li UOPS_ISSUED.SINGLE_MUL
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.Pq Event 0EH , Umask 40H
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Number of multiply packed/scalar single precision uops allocated.
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.It Li ARITH.FPU_DIV_ACTIVE
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.Pq Event 14H , Umask 01H
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Cycles that the divider is active, includes INT and FP. Set 'edge =1,
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cmask=1' to count the number of divides.
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.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
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.Pq Event 24H , Umask 01H
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Demand Data Read requests that hit L2 cache.
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.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
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.Pq Event 24H , Umask 03H
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Counts any demand and L1 HW prefetch data load requests to L2.
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.It Li L2_RQSTS.RFO_HITS
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.Pq Event 24H , Umask 04H
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Counts the number of store RFO requests that hit the L2 cache.
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.It Li L2_RQSTS.RFO_MISS
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.Pq Event 24H , Umask 08H
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Counts the number of store RFO requests that miss the L2 cache.
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.It Li L2_RQSTS.ALL_RFO
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.Pq Event 24H , Umask 0CH
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Counts all L2 store RFO requests.
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.It Li L2_RQSTS.CODE_RD_HIT
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.Pq Event 24H , Umask 10H
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Number of instruction fetches that hit the L2 cache.
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.It Li L2_RQSTS.CODE_RD_MISS
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.Pq Event 24H , Umask 20H
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Number of instruction fetches that missed the L2 cache.
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.It Li L2_RQSTS.ALL_CODE_RD
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.Pq Event 24H , Umask 30H
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Counts all L2 code requests.
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.It Li L2_RQSTS.PF_HIT
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.Pq Event 24H , Umask 40H
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Counts all L2 HW prefetcher requests that hit L2.
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.It Li L2_RQSTS.PF_MISS
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.Pq Event 24H , Umask 80H
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Counts all L2 HW prefetcher requests that missed L2.
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.It Li L2_RQSTS.ALL_PF
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.Pq Event 24H , Umask C0H
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Counts all L2 HW prefetcher requests.
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.It Li L2_STORE_LOCK_RQSTS.MISS
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.Pq Event 27H , Umask 01H
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RFOs that miss cache lines.
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.It Li L2_STORE_LOCK_RQSTS.HIT_M
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.Pq Event 27H , Umask 08H
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RFOs that hit cache lines in M state.
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.It Li L2_STORE_LOCK_RQSTS.ALL
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.Pq Event 27H , Umask 0FH
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RFOs that access cache lines in any state.
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.It Li L2_L1D_WB_RQSTS.MISS
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.Pq Event 28H , Umask 01H
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Not rejected writebacks that missed LLC.
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.It Li L2_L1D_WB_RQSTS.HIT_E
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.Pq Event 28H , Umask 04H
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Not rejected writebacks from L1D to L2 cache lines in E state.
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.It Li L2_L1D_WB_RQSTS.HIT_M
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.Pq Event 28H , Umask 08H
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Not rejected writebacks from L1D to L2 cache lines in M state.
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.It Li L2_L1D_WB_RQSTS.ALL
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.Pq Event 28H , Umask 0FH
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Not rejected writebacks from L1D to L2 cache lines in any state.
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.It Li LONGEST_LAT_CACHE.REFERENCE
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.Pq Event 2EH , Umask 4FH
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This event counts requests originating from the core that reference a cache
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line in the last level cache.
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.It Li LONGEST_LAT_CACHE.MISS
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.Pq Event 2EH , Umask 41H
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This event counts each cache miss condition for references to the last level
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cache.
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.It Li CPU_CLK_UNHALTED.THREAD_P
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.Pq Event 3CH , Umask 00H
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Counts the number of thread cycles while the thread is not in a halt state.
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The thread enters the halt state when it is running the HLT instruction. The
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core frequency may change from time to time due to power or thermal
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throttling.
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.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
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.Pq Event 3CH , Umask 01H
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Increments at the frequency of XCLK (100 MHz) when not halted.
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.It Li L1D_PEND_MISS.PENDING
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.Pq Event 48H , Umask 01H
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Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1
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and Edge =1 to count occurrences.
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Counter 2 only.
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Set Cmask = 1 to count cycles.
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.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 49H , Umask 01H
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Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
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.It Li DTLB_STORE_MISSES.WALK_COMPLETED
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.Pq Event 49H , Umask 02H
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Miss in all TLB levels causes a page walk that completes of any page size
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(4K/2M/4M/1G).
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.It Li DTLB_STORE_MISSES.WALK_DURATION
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.Pq Event 49H , Umask 04H
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Cycles PMH is busy with this walk.
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.It Li DTLB_STORE_MISSES.STLB_HIT
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.Pq Event 49H , Umask 10H
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Store operations that miss the first TLB level but hit the second and do not
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cause page walks.
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.It Li LOAD_HIT_PRE.SW_PF
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.Pq Event 4CH , Umask 01H
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Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
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.It Li LOAD_HIT_PRE.HW_PF
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.Pq Event 4CH , Umask 02H
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Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
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.It Li L1D.REPLACEMENT
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.Pq Event 51H , Umask 01H
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Counts the number of lines brought into the L1 data cache.
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.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
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.Pq Event 58H , Umask 01H
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Number of integer Move Elimination candidate uops that were not eliminated.
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.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
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.Pq Event 58H , Umask 02H
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Number of SIMD Move Elimination candidate uops that were not eliminated.
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.It Li MOVE_ELIMINATION.INT_ELIMINATED
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.Pq Event 58H , Umask 04H
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Number of integer Move Elimination candidate uops that were eliminated.
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.It Li MOVE_ELIMINATION.SIMD_ELIMINATED
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.Pq Event 58H , Umask 08H
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Number of SIMD Move Elimination candidate uops that were eliminated.
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.It Li CPL_CYCLES.RING0
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.Pq Event 5CH , Umask 01H
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Unhalted core cycles when the thread is in ring 0.
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Use Edge to count transition.
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.It Li CPL_CYCLES.RING123
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.Pq Event 5CH , Umask 02H
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Unhalted core cycles when the thread is not in ring 0.
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.It Li RS_EVENTS.EMPTY_CYCLES
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.Pq Event 5EH , Umask 01H
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Cycles the RS is empty for the thread.
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.It Li DTLB_LOAD_MISSES.STLB_HIT
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.Pq Event 5FH , Umask 04H
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Counts load operations that missed 1st level DTLB but hit the 2nd level.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
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.Pq Event 60H , Umask 01H
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Offcore outstanding Demand Data Read transactions in SQ to uncore. Set
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Cmask=1 to count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
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.Pq Event 60H , Umask 02H
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Offcore outstanding Demand Code Read transactions in SQ to uncore. Set
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Cmask=1 to count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
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.Pq Event 60H , Umask 04H
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Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to
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count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
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.Pq Event 60H , Umask 08H
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Offcore outstanding cacheable data read transactions in SQ to uncore. Set
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Cmask=1 to count cycles.
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.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
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.Pq Event 63H , Umask 01H
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Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
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.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
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.Pq Event 63H , Umask 02H
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Cycles in which the L1D is locked.
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.It Li IDQ.EMPTY
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.Pq Event 79H , Umask 02H
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Counts cycles the IDQ is empty.
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.It Li IDQ.MITE_UOPS
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.Pq Event 79H , Umask 04H
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Increment each cycle # of uops delivered to IDQ from MITE path.
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Can combine Umask 04H and 20H.
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Set Cmask = 1 to count cycles.
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.It Li IDQ.DSB_UOPS
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.Pq Event 79H , Umask 08H
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Increment each cycle. # of uops delivered to IDQ from DSB path.
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Can combine Umask 08H and 10H
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Set Cmask = 1 to count cycles.
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.It Li IDQ.MS_DSB_UOPS
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.Pq Event 79H , Umask 10H
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Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set
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Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
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Can combine Umask 04H, 08H.
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.It Li IDQ.MS_MITE_UOPS
|
|
.Pq Event 79H , Umask 20H
|
|
Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set
|
|
Cmask = 1 to count cycles.
|
|
Can combine Umask 04H, 08H.
|
|
.It Li IDQ.MS_UOPS
|
|
.Pq Event 79H , Umask 30H
|
|
Increment each cycle # of uops delivered to IDQ from MS by either DSB or
|
|
MITE. Set Cmask = 1 to count cycles.
|
|
Can combine Umask 04H, 08H.
|
|
.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
|
|
.Pq Event 79H , Umask 18H
|
|
Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
|
|
.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
|
|
.Pq Event 79H , Umask 18H
|
|
Counts cycles DSB is delivered four uops. Set Cmask = 4.
|
|
.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
|
|
.Pq Event 79H , Umask 24H
|
|
Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
|
|
.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
|
|
.Pq Event 79H , Umask 24H
|
|
Counts cycles MITE is delivered four uops. Set Cmask = 4.
|
|
.It Li IDQ.MITE_ALL_UOPS
|
|
.Pq Event 79H , Umask 3CH
|
|
# of uops delivered to IDQ from any path.
|
|
.It Li ICACHE.MISSES
|
|
.Pq Event 80H , Umask 02H
|
|
Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
|
|
Includes UC accesses.
|
|
.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
|
|
.Pq Event 85H , Umask 01H
|
|
Misses in all ITLB levels that cause page walks.
|
|
.It Li ITLB_MISSES.WALK_COMPLETED
|
|
.Pq Event 85H , Umask 02H
|
|
Misses in all ITLB levels that cause completed page walks.
|
|
.It Li ITLB_MISSES.WALK_DURATION
|
|
.Pq Event 85H , Umask 04H
|
|
Cycle PMH is busy with a walk.
|
|
.It Li ITLB_MISSES.STLB_HIT
|
|
.Pq Event 85H , Umask 10H
|
|
Number of cache load STLB hits. No page walk.
|
|
.It Li ILD_STALL.LCP
|
|
.Pq Event 87H , Umask 01H
|
|
Stalls caused by changing prefix length of the instruction.
|
|
.It Li ILD_STALL.IQ_FULL
|
|
.Pq Event 87H , Umask 04H
|
|
Stall cycles due to IQ is full.
|
|
.It Li BR_INST_EXEC.NONTAKEN_COND
|
|
.Pq Event 88H , Umask 41H
|
|
Count conditional near branch instructions that were executed (but not
|
|
necessarily retired) and not taken.
|
|
.It Li BR_INST_EXEC.TAKEN_COND
|
|
.Pq Event 88H , Umask 81H
|
|
Count conditional near branch instructions that were executed (but not
|
|
necessarily retired) and taken.
|
|
.It Li BR_INST_EXEC.DIRECT_JMP
|
|
.Pq Event 88H , Umask 82H
|
|
Count all unconditional near branch instructions excluding calls and
|
|
indirect branches.
|
|
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
|
.Pq Event 88H , Umask 84H
|
|
Count executed indirect near branch instructions that are not calls nor
|
|
returns.
|
|
.It Li BR_INST_EXEC.RETURN_NEAR
|
|
.Pq Event 88H , Umask 88H
|
|
Count indirect near branches that have a return mnemonic.
|
|
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
|
.Pq Event 88H , Umask 90H
|
|
Count unconditional near call branch instructions, excluding non call
|
|
branch, executed.
|
|
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
|
.Pq Event 88H , Umask A0H
|
|
Count indirect near calls, including both register and memory indirect,
|
|
executed.
|
|
.It Li BR_INST_EXEC.ALL_BRANCHES
|
|
.Pq Event 88H , Umask FFH
|
|
Counts all near executed branches (not necessarily retired).
|
|
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
|
.Pq Event 89H , Umask 41H
|
|
Count conditional near branch instructions mispredicted as nontaken.
|
|
.It Li BR_MISP_EXEC.TAKEN_COND
|
|
.Pq Event 89H , Umask 81H
|
|
Count conditional near branch instructions mispredicted as taken.
|
|
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
|
.Pq Event 89H , Umask 84H
|
|
Count mispredicted indirect near branch instructions that are not calls
|
|
nor returns.
|
|
.It Li BR_MISP_EXEC.RETURN_NEAR
|
|
.Pq Event 89H , Umask 88H
|
|
Count mispredicted indirect near branches that have a return mnemonic.
|
|
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
|
.Pq Event 89H , Umask 90H
|
|
Count mispredicted unconditional near call branch instructions, excluding
|
|
non call branch, executed.
|
|
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
|
.Pq Event 89H , Umask A0H
|
|
Count mispredicted indirect near calls, including both register and memory
|
|
indirect, executed.
|
|
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
|
.Pq Event 89H , Umask FFH
|
|
Counts all mispredicted near executed branches (not necessarily retired).
|
|
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
|
.Pq Event 9CH , Umask 01H
|
|
Count number of non-delivered uops to RAT per thread.
|
|
Use Cmask to qualify uop b/w.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_0
|
|
.Pq Event A1H , Umask 01H
|
|
Cycles which a Uop is dispatched on port 0.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_1
|
|
.Pq Event A1H , Umask 02H
|
|
Cycles which a Uop is dispatched on port 1.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
|
|
.Pq Event A1H , Umask 04H
|
|
Cycles which a load uop is dispatched on port 2.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
|
|
.Pq Event A1H , Umask 08H
|
|
Cycles which a store address uop is dispatched on port 2.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_2
|
|
.Pq Event A1H , Umask 0CH
|
|
Cycles which a Uop is dispatched on port 2.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
|
|
.Pq Event A1H , Umask 10H
|
|
Cycles which a load uop is dispatched on port 3.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
|
|
.Pq Event A1H , Umask 20H
|
|
Cycles which a store address uop is dispatched on port 3.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_3
|
|
.Pq Event A1H , Umask 30H
|
|
Cycles which a Uop is dispatched on port 3.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_4
|
|
.Pq Event A1H , Umask 40H
|
|
Cycles which a Uop is dispatched on port 4.
|
|
.It Li UOPS_DISPATCHED_PORT.PORT_5
|
|
.Pq Event A1H , Umask 80H
|
|
Cycles which a Uop is dispatched on port 5.
|
|
.It Li RESOURCE_STALLS.ANY
|
|
.Pq Event A2H , Umask 01H
|
|
Cycles Allocation is stalled due to Resource Related reason.
|
|
.It Li RESOURCE_STALLS.RS
|
|
.Pq Event A2H , Umask 04H
|
|
Cycles stalled due to no eligible RS entry available.
|
|
.It Li RESOURCE_STALLS.SB
|
|
.Pq Event A2H , Umask 08H
|
|
Cycles stalled due to no store buffers available. (not including draining
|
|
form sync).
|
|
.It Li RESOURCE_STALLS.ROB
|
|
.Pq Event A2H , Umask 10H
|
|
Cycles stalled due to re-order buffer full.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
|
|
.Pq Event A3H , Umask 01H
|
|
Cycles with pending L2 miss loads. Set AnyThread to count per core.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING
|
|
.Pq Event A3H , Umask 02H
|
|
Cycles with pending memory loads. Set AnyThread to count per core.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_NO_EXECUTE
|
|
.Pq Event A3H , Umask 04H
|
|
Cycles of dispatch stalls. Set AnyThread to count per core.
|
|
.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
|
|
.Pq Event A3H , Umask 08H
|
|
Cycles with pending L1 cache miss loads. Set AnyThread to count per core.
|
|
.It Li DSB2MITE_SWITCHES.COUNT
|
|
.Pq Event ABH , Umask 01H
|
|
Number of DSB to MITE switches.
|
|
.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
|
|
.Pq Event ABH , Umask 02H
|
|
Cycles DSB to MITE switches caused delay.
|
|
.It Li DSB_FILL.EXCEED_DSB_LINES
|
|
.Pq Event ACH , Umask 08H
|
|
DSB Fill encountered > 3 DSB lines.
|
|
.It Li ITLB.ITLB_FLUSH
|
|
.Pq Event AEH , Umask 01H
|
|
Counts the number of ITLB flushes, includes 4k/2M/4M pages.
|
|
.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
|
|
.Pq Event B0H , Umask 01H
|
|
Demand data read requests sent to uncore.
|
|
.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
|
|
.Pq Event B0H , Umask 02H
|
|
Demand code read requests sent to uncore.
|
|
.It Li OFFCORE_REQUESTS.DEMAND_RFO
|
|
.Pq Event B0H , Umask 04H
|
|
Demand RFO read requests sent to uncore, including regular RFOs, locks,
|
|
ItoM.
|
|
.It Li OFFCORE_REQUESTS.ALL_DATA_RD
|
|
.Pq Event B0H , Umask 08H
|
|
Data read requests sent to uncore (demand and prefetch).
|
|
.It Li UOPS_EXECUTED.THREAD
|
|
.Pq Event B1H , Umask 01H
|
|
Counts total number of uops to be executed per-thread each cycle. Set Cmask
|
|
= 1, INV =1 to count stall cycles.
|
|
.It Li UOPS_EXECUTED.CORE
|
|
.Pq Event B1H , Umask 02H
|
|
Counts total number of uops to be executed per-core each cycle.
|
|
Do not need to set ANY.
|
|
.It Li OFF_CORE_RESPONSE_0
|
|
.Pq Event B7H , Umask 01H
|
|
Off-core Response Performance Monitoring.
|
|
PMC0 only.
|
|
Requires programming MSR 01A6H.
|
|
.It Li OFF_CORE_RESPONSE_1
|
|
.Pq Event BBH , Umask 01H
|
|
Off-core Response Performance Monitoring.
|
|
PMC3 only.
|
|
Requires programming MSR 01A7H.
|
|
.It Li TLB_FLUSH.DTLB_THREAD
|
|
.Pq Event BDH , Umask 01H
|
|
DTLB flush attempts of the thread- specific entries.
|
|
.It Li TLB_FLUSH.STLB_ANY
|
|
.Pq Event BDH , Umask 20H
|
|
Count number of STLB flush attempts.
|
|
.It Li INST_RETIRED.ANY_P
|
|
.Pq Event C0H , Umask 00H
|
|
Number of instructions at retirement.
|
|
.It Li INST_RETIRED.ALL
|
|
.Pq Event C0H , Umask 01H
|
|
Precise instruction retired event with HW to reduce effect of PEBS shadow in
|
|
IP distribution.
|
|
PMC1 only.
|
|
Must quiesce other PMCs.
|
|
.It Li OTHER_ASSISTS.AVX_STORE
|
|
.Pq Event C1H , Umask 08H
|
|
Number of assists associated with 256-bit AVX store operations.
|
|
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
|
.Pq Event C1H , Umask 10H
|
|
Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
|
|
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
|
.Pq Event C1H , Umask 20H
|
|
Number of transitions from SSE to AVX-256 when penalty applicable.
|
|
.It Li UOPS_RETIRED.ALL
|
|
.Pq Event C2H , Umask 01H
|
|
Counts the number of micro-ops retired, Use cmask=1 and invert to count
|
|
active cycles or stalled cycles.
|
|
Supports PEBS, use Any=1 for core granular.
|
|
.It Li UOPS_RETIRED.RETIRE_SLOTS
|
|
.Pq Event C2H , Umask 02H
|
|
Counts the number of retirement slots used each cycle.
|
|
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
|
.Pq Event C3H , Umask 02H
|
|
Counts the number of machine clears due to memory order conflicts.
|
|
.It Li MACHINE_CLEARS.SMC
|
|
.Pq Event C3H , Umask 04H
|
|
Number of self-modifying-code machine clears detected.
|
|
.It Li MACHINE_CLEARS.MASKMOV
|
|
.Pq Event C3H , Umask 20H
|
|
Counts the number of executed AVX masked load operations that refer to an
|
|
illegal address range with the mask bits set to 0.
|
|
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
|
.Pq Event C4H , Umask 00H
|
|
Branch instructions at retirement.
|
|
.It Li BR_INST_RETIRED.CONDITIONAL
|
|
.Pq Event C4H , Umask 01H
|
|
Counts the number of conditional branch instructions retired.
|
|
Supports PEBS.
|
|
.It Li BR_INST_RETIRED.NEAR_CALL
|
|
.Pq Event C4H , Umask 02H
|
|
Direct and indirect near call instructions retired.
|
|
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
|
.Pq Event C4H , Umask 04H
|
|
Counts the number of branch instructions retired.
|
|
.It Li BR_INST_RETIRED.NEAR_RETURN
|
|
.Pq Event C4H , Umask 08H
|
|
Counts the number of near return instructions retired.
|
|
.It Li BR_INST_RETIRED.NOT_TAKEN
|
|
.Pq Event C4H , Umask 10H
|
|
Counts the number of not taken branch instructions retired.
|
|
.It Li BR_INST_RETIRED.NEAR_TAKEN
|
|
.Pq Event C4H , Umask 20H
|
|
Number of near taken branches retired.
|
|
.It Li BR_INST_RETIRED.FAR_BRANCH
|
|
.Pq Event C4H , Umask 40H
|
|
Number of far branches retired.
|
|
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
|
.Pq Event C5H , Umask 00H
|
|
Mispredicted branch instructions at retirement.
|
|
.It Li BR_MISP_RETIRED.CONDITIONAL
|
|
.Pq Event C5H , Umask 01H
|
|
Mispredicted conditional branch instructions retired.
|
|
Supports PEBS.
|
|
.It Li BR_MISP_RETIRED.NEAR_CALL
|
|
.Pq Event C5H , Umask 02H
|
|
Direct and indirect mispredicted near call instructions retired.
|
|
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
|
.Pq Event C5H , Umask 04H
|
|
Mispredicted macro branch instructions retired.
|
|
.It Li BR_MISP_RETIRED.NOT_TAKEN
|
|
.Pq Event C5H , Umask 10H
|
|
Mispredicted not taken branch instructions retired.
|
|
.It Li BR_MISP_RETIRED.TAKEN
|
|
.Pq Event C5H , Umask 20H
|
|
Mispredicted taken branch instructions retired.
|
|
.It Li FP_ASSIST.X87_OUTPUT
|
|
.Pq Event CAH , Umask 02H
|
|
Number of X87 FP assists due to Output values.
|
|
.It Li FP_ASSIST.X87_INPUT
|
|
.Pq Event CAH , Umask 04H
|
|
Number of X87 FP assists due to input values.
|
|
.It Li FP_ASSIST.SIMD_OUTPUT
|
|
.Pq Event CAH , Umask 08H
|
|
Number of SIMD FP assists due to Output values.
|
|
.It Li FP_ASSIST.SIMD_INPUT
|
|
.Pq Event CAH , Umask 10H
|
|
Number of SIMD FP assists due to input values.
|
|
.It Li FP_ASSIST.ANY
|
|
.Pq Event CAH , Umask 1EH
|
|
Cycles with any input/output SSE* or FP assists.
|
|
.It Li ROB_MISC_EVENTS.LBR_INSERTS
|
|
.Pq Event CCH , Umask 20H
|
|
Count cases of saving new LBR records by hardware.
|
|
.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
|
|
.Pq Event CDH , Umask 01H
|
|
Sample loads with specified latency threshold.
|
|
PMC3 only.
|
|
Specify threshold in MSR 0x3F6.
|
|
.It Li MEM_TRANS_RETIRED.PRECISE_STORE
|
|
.Pq Event CDH , Umask 02H
|
|
Sample stores and collect precise store operation via PEBS record.
|
|
PMC3 only.
|
|
.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
|
|
.Pq Event D0H , Umask 11H
|
|
Count retired load uops that missed the STLB.
|
|
.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
|
|
.Pq Event D0H , Umask 12H
|
|
Count retired store uops that missed the STLB.
|
|
.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
|
|
.Pq Event D0H , Umask 41H
|
|
Count retired load uops that were split across a cache line.
|
|
.It Li MEM_UOPS_RETIRED.SPLIT_STORES
|
|
.Pq Event D0H , Umask 42H
|
|
Count retired store uops that were split across a cache line.
|
|
.It Li MEM_UOPS_RETIRED.ALL_LOADS
|
|
.Pq Event D0H , Umask 81H
|
|
Count all retired load uops.
|
|
.It Li MEM_UOPS_RETIRED.ALL_STORES
|
|
.Pq Event D0H , Umask 82H
|
|
Count all retired store uops.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
|
.Pq Event D1H , Umask 01H
|
|
Retired load uops with L1 cache hits as data sources.
|
|
Supports PEBS.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
|
.Pq Event D1H , Umask 02H
|
|
Retired load uops with L2 cache hits as data sources.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
|
.Pq Event D1H , Umask 04H
|
|
Retired load uops whose data source was LLC hit with no snoop required.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS
|
|
.Pq Event D1H , Umask 20H
|
|
Retired load uops whose data source is LLC miss.
|
|
.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
|
.Pq Event D1H , Umask 40H
|
|
Retired load uops which data sources were load uops missed L1 but hit FB due
|
|
to preceding miss to the same cache line with data not ready.
|
|
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
|
|
.Pq Event D2H , Umask 01H
|
|
Retired load uops which data sources were LLC hit and cross-core snoop
|
|
missed in on-pkg core cache.
|
|
Supports PEBS.
|
|
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
|
|
.Pq Event D2H , Umask 02H
|
|
Retired load uops which data sources were LLC and cross-core snoop hits in
|
|
on-pkg core cache.
|
|
Supports PEBS.
|
|
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
|
|
.Pq Event D2H , Umask 04H
|
|
Retired load uops which data sources were HitM responses from shared LLC.
|
|
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
|
|
.Pq Event D2H , Umask 08H
|
|
Retired load uops which data sources were hits in LLC without snoops
|
|
required.
|
|
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
|
|
.Pq Event D3H , Umask 01H
|
|
Retired load uops which data sources missed LLC but serviced from local
|
|
dram.
|
|
Supports PEBS.
|
|
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM
|
|
.Pq Event D3H , Umask 04H
|
|
Retired load uops whose data source was remote DRAM.
|
|
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM
|
|
.Pq Event D3H , Umask 10H
|
|
Retired load uops whose data source was remote HITM.
|
|
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD
|
|
.Pq Event D3H , Umask 20H
|
|
Retired load uops whose data source was forwards from a remote cache.
|
|
.It Li BACLEARS.ANY
|
|
.Pq Event E6H , Umask 1FH
|
|
Number of front end re-steers due to BPU misprediction.
|
|
.It Li L2_TRANS.DEMAND_DATA_RD
|
|
.Pq Event F0H , Umask 01H
|
|
Demand Data Read requests that access L2 cache.
|
|
.It Li L2_TRANS.RFO
|
|
.Pq Event F0H , Umask 02H
|
|
RFO requests that access L2 cache.
|
|
.It Li L2_TRANS.CODE_RD
|
|
.Pq Event F0H , Umask 04H
|
|
L2 cache accesses when fetching instructions.
|
|
.It Li L2_TRANS.ALL_PF
|
|
.Pq Event F0H , Umask 08H
|
|
Any MLC or LLC HW prefetch accessing L2, including rejects.
|
|
.It Li L2_TRANS.L1D_WB
|
|
.Pq Event F0H , Umask 10H
|
|
L1D writebacks that access L2 cache.
|
|
.It Li L2_TRANS.L2_FILL
|
|
.Pq Event F0H , Umask 20H
|
|
L2 fill requests that access L2 cache.
|
|
.It Li L2_TRANS.L2_WB
|
|
.Pq Event F0H , Umask 40H
|
|
L2 writebacks that access L2 cache.
|
|
.It Li L2_TRANS.ALL_REQUESTS
|
|
.Pq Event F0H , Umask 80H
|
|
Transactions accessing L2 pipe.
|
|
.It Li L2_LINES_IN.I
|
|
.Pq Event F1H , Umask 01H
|
|
L2 cache lines in I state filling L2.
|
|
Counting does not cover rejects.
|
|
.It Li L2_LINES_IN.S
|
|
.Pq Event F1H , Umask 02H
|
|
L2 cache lines in S state filling L2.
|
|
Counting does not cover rejects.
|
|
.It Li L2_LINES_IN.E
|
|
.Pq Event F1H , Umask 04H
|
|
L2 cache lines in E state filling L2.
|
|
Counting does not cover rejects.
|
|
.It Li L2_LINES_IN.ALL
|
|
.Pq Event F1H , Umask 07H
|
|
L2 cache lines filling L2.
|
|
Counting does not cover rejects.
|
|
.It Li L2_LINES_OUT.DEMAND_CLEAN
|
|
.Pq Event F2H , Umask 01H
|
|
Clean L2 cache lines evicted by demand.
|
|
.It Li L2_LINES_OUT.DEMAND_DIRTY
|
|
.Pq Event F2H , Umask 02H
|
|
Dirty L2 cache lines evicted by demand.
|
|
.It Li L2_LINES_OUT.PF_CLEAN
|
|
.Pq Event F2H , Umask 04H
|
|
Clean L2 cache lines evicted by the MLC prefetcher.
|
|
.It Li L2_LINES_OUT.PF_DIRTY
|
|
.Pq Event F2H , Umask 08H
|
|
Dirty L2 cache lines evicted by the MLC prefetcher.
|
|
.It Li L2_LINES_OUT.DIRTY_ALL
|
|
.Pq Event F2H , Umask 0AH
|
|
Dirty L2 cache lines filling the L2.
|
|
.El
|
|
.Sh SEE ALSO
|
|
.Xr pmc 3 ,
|
|
.Xr pmc.atom 3 ,
|
|
.Xr pmc.core 3 ,
|
|
.Xr pmc.corei7 3 ,
|
|
.Xr pmc.corei7uc 3 ,
|
|
.Xr pmc.iaf 3 ,
|
|
.Xr pmc.ivybridge 3 ,
|
|
.Xr pmc.k7 3 ,
|
|
.Xr pmc.k8 3 ,
|
|
.Xr pmc.p4 3 ,
|
|
.Xr pmc.p5 3 ,
|
|
.Xr pmc.p6 3 ,
|
|
.Xr pmc.sandybridge 3 ,
|
|
.Xr pmc.sandybridgeuc 3 ,
|
|
.Xr pmc.sandybridgexeon 3 ,
|
|
.Xr pmc.soft 3 ,
|
|
.Xr pmc.tsc 3 ,
|
|
.Xr pmc.ucf 3 ,
|
|
.Xr pmc.westmere 3 ,
|
|
.Xr pmc.westmereuc 3 ,
|
|
.Xr pmc_cpuinfo 3 ,
|
|
.Xr pmclog 3 ,
|
|
.Xr hwpmc 4
|
|
.Sh HISTORY
|
|
The
|
|
.Nm pmc
|
|
library first appeared in
|
|
.Fx 6.0 .
|
|
.Sh AUTHORS
|
|
.An -nosplit
|
|
The
|
|
.Lb libpmc
|
|
library was written by
|
|
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
|
The support for the Ivy Bridge Xeon
|
|
microarchitecture was written by
|
|
.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com .
|