267 lines
9.8 KiB
C
267 lines
9.8 KiB
C
/* Opcode table for the H8-300
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Copyright (C) 1991,1992 Free Software Foundation.
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Written by Steve Chamberlain, sac@cygnus.com.
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This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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typedef int op_type;
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#define Hex0 0
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#define Hex1 1
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#define Hex2 2
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#define Hex3 3
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#define Hex4 4
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#define Hex5 5
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#define Hex6 6
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#define Hex7 7
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#define Hex8 8
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#define Hex9 9
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#define HexA 10
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#define HexB 11
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#define HexC 12
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#define HexD 13
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#define HexE 14
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#define HexF 15
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#define START 0x20
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#define KBIT 0x21 /* K is #1, or #2, yielding 0x0 or 0x8 */
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#define IMM3 0x22 /* bit number */
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#define RD8 0x23 /* 8 bit reg as 2nd op */
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#define RD16 0x24 /* 16 bit reg as 2nd op */
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#define RS8 0x25 /* 8 bit reg as 1st op */
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#define RS16 0x26 /* 16 bit reg 1st op */
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#define IMM8 0x27 /* constant which fits into 8 bits */
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#define IMM16 0x28 /* constant which fits into 16 bits */
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#define CCR 0x29 /* CCR reg */
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#define ABS8SRC 0x2a /* abs 8 address mode */
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#define ABS8DST 0x2b /* abs 8 address mode */
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#define DISP8 0x2c /* pc rel displacement */
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#define ABS16SRC 0x2d /* abs 16 address mode */
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#define ABS16OR8SRC 0x2e /* abs 16 address mode, but could be abs 8 */
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#define ABS16DST 0x2f /* abs 16 address mode */
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#define ABS16OR8DST 0x30 /* abs 16 address mode */
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#define DISPSRC 0x31 /* @(r:16) address mode src */
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#define DISPDST 0x32 /* @(r:16) address mode dst*/
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#define DISPREG 0x33 /* register from DISP address mode */
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#define RDDEC 0x34 /* @-rn mode */
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#define RSINC 0x35 /* @rn+ mode */
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#define RDIND 0x36 /* @R mode dst */
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#define RSIND 0x37 /* @R mode src */
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#define MEMIND 0x38 /* @@abs8 mode */
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#define ABS16ORREL8SRC 0x39 /* abs 16bit or pcrel */
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#define IGNORE 0x3a
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#define B30 0x40 /* bit 3 must be low */
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#define B31 0x80 /* bit 3 must be high */
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#define E 0x81 /* End of list */
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struct code
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{
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op_type nib[9];
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} ;
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struct arg
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{
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op_type nib[3];
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} ;
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struct h8_opcode
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{
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char *name;
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struct arg args;
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struct code data;
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char length;
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char noperands;
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char idx;
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char size;
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};
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#ifdef DEFINE_TABLE
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#define BITOP(imm, name, op00, op01,op10,op11, op20,op21)\
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{ name, {imm,RD8,E}, {op00, op01, imm, RD8,E}},\
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{ name, {imm,RDIND,E}, {op10, op11, RDIND, 0, op00,op01, imm, 0,E}},\
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{ name, {imm,ABS8DST,E},{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}
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#define EBITOP(imm, name, op00, op01,op10,op11, op20,op21)\
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BITOP(imm, name, op00+1, op01, op10,op11, op20,op21),\
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BITOP(RS8, name, op00, op01, op10,op11, op20,op21)
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#define WTWOP(name, op1, op2) \
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{ name, {RS16, RD16, E}, { op1, op2, RS16, RD16, E}}
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#define BRANCH(name, op) \
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{ name,{DISP8,E}, { Hex4, op, DISP8,IGNORE,E }}
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#define SOP(name) \
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{ name
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#define EOP }
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#define TWOOP(name, op1, op2,op3) \
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{ name, {IMM8, RD8,E}, { op1, RD8, IMM8,IGNORE,E}},\
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{ name, {RS8, RD8, E}, { op2, op3, RS8, RD8 ,E}}
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#define UNOP(name, op1, op2) \
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{ name, {RS8, E}, { op1, op2, 0, RS8, E}}
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#define UNOP3(name, op1, op2, op3) \
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{ name , {RS8, E}, {op1, op2, op3, RS8, E}}
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struct h8_opcode h8_opcodes[]
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=
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{
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TWOOP("add.b", Hex8, Hex0,Hex8),
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WTWOP("add.w", Hex0, Hex9),
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SOP("adds"), {KBIT,RD16|B30, E}, {Hex0, HexB, KBIT, RD16|B30, E} EOP,
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TWOOP("addx", Hex9,Hex0,HexE),
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TWOOP("and", HexE,Hex1,Hex6),
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SOP("andc"), {IMM8, CCR, E}, { Hex0, Hex6, IMM8,IGNORE, E} EOP,
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BITOP(IMM3|B30, "band", Hex7, Hex6, Hex7, HexC, Hex7, HexE),
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BRANCH("bra", Hex0),
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BRANCH("bt", Hex0),
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BRANCH("brn", Hex1),
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BRANCH("bf", Hex1),
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BRANCH("bhi", Hex2),
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BRANCH("bls", Hex3),
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BRANCH("bcc", Hex4),
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BRANCH("bhs", Hex4),
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BRANCH("bcs", Hex5),
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BRANCH("blo", Hex5),
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BRANCH("bne", Hex6),
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BRANCH("beq", Hex7),
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BRANCH("bvc", Hex8),
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BRANCH("bvs", Hex9),
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BRANCH("bpl", HexA),
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BRANCH("bmi", HexB),
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BRANCH("bge", HexC),
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BRANCH("blt", HexD),
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BRANCH("bgt", HexE),
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BRANCH("ble", HexF),
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EBITOP(IMM3|B30,"bclr", Hex6, Hex2, Hex7, HexD, Hex7, HexF),
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BITOP(IMM3|B31,"biand", Hex7, Hex6, Hex7, HexC, Hex7, HexE),
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BITOP(IMM3|B31, "bild", Hex7, Hex7,Hex7, HexC, Hex7, HexE),
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BITOP(IMM3|B31, "bior", Hex7, Hex4,Hex7, HexC, Hex7, HexE),
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BITOP(IMM3|B31, "bist", Hex6, Hex7,Hex7, HexD, Hex7, HexE),
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BITOP(IMM3|B31, "bixor", Hex7, Hex5,Hex7, HexC, Hex7, HexE),
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BITOP(IMM3|B30, "bld", Hex7, Hex7,Hex7, HexC, Hex7, HexE),
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EBITOP(IMM3|B30,"bnot", Hex6, Hex1, Hex7, HexD, Hex7, HexF),
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BITOP(IMM3|B30,"bor", Hex7, Hex4,Hex7, HexC, Hex7, HexE),
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EBITOP(IMM3|B30,"bset", Hex6, Hex0,Hex7, HexD, Hex7, HexF),
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SOP("bsr"),{DISP8, E},{ Hex5, Hex5, DISP8,IGNORE, E}, EOP,
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BITOP(IMM3|B30, "bst", Hex6, Hex7,Hex7, HexD, Hex7, HexF),
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EBITOP(IMM3|B30, "btst", Hex6, Hex3,Hex7, HexC, Hex7, HexE),
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BITOP(IMM3|B30, "bxor", Hex7,Hex5,Hex7, HexC, Hex7, HexE),
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TWOOP( "cmp.b",HexA, Hex1, HexC),
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WTWOP( "cmp.w",Hex1,HexD),
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UNOP( "daa",Hex0, HexF),
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UNOP( "das",Hex1, HexF),
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UNOP( "dec",Hex1, HexA),
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SOP("divxu"),{RS8, RD16|B30, E}, { Hex5, Hex1, RS8, RD16|B30, E} EOP,
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SOP("eepmov"),{ E}, {Hex7, HexB, Hex5, HexC, Hex5, Hex9, Hex8, HexF,E} EOP,
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UNOP( "inc", Hex0, HexA),
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SOP("jmp"),{RSIND|B30, E}, {Hex5, Hex9, RSIND|B30, Hex0, E} EOP,
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SOP("jmp"),{ABS16ORREL8SRC, E}, {Hex5, HexA, Hex0, Hex0, ABS16ORREL8SRC, IGNORE,IGNORE,IGNORE,E} EOP,
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SOP("jmp"),{MEMIND, E}, {Hex5, HexB, MEMIND,IGNORE, E} EOP,
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SOP("jsr"),{RSIND|B30, E}, {Hex5, HexD, RSIND|B30, Hex0, E} EOP,
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SOP("jsr"),{ABS16ORREL8SRC, E}, {Hex5, HexE, Hex0, Hex0,
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ABS16ORREL8SRC,IGNORE,IGNORE,IGNORE, E} EOP,
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SOP("jsr"),{MEMIND, E}, {Hex5, HexF, MEMIND, IGNORE,E} EOP,
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SOP("ldc"),{IMM8, CCR, E}, { Hex0, Hex7, IMM8,IGNORE, E} EOP,
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SOP("ldc"),{RS8, CCR, E}, { Hex0, Hex3, Hex0, RS8, E} EOP,
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SOP("mov.b"),{RS8, RD8, E}, { Hex0, HexC, RS8, RD8, E} EOP,
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SOP("mov.b"),{IMM8, RD8, E}, { HexF, RD8, IMM8,IGNORE, E} EOP,
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SOP("mov.b"),{RSIND|B30,RD8, E}, { Hex6, Hex8, RSIND|B30, RD8, E} EOP,
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SOP("mov.b"),{DISPSRC,RD8, E}, { Hex6, HexE, DISPREG|B30, RD8,
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DISPSRC, IGNORE, IGNORE, IGNORE, E} EOP,
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SOP("mov.b"),{RSINC|B30, RD8, E}, { Hex6, HexC, RSINC|B30, RD8, E} EOP,
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SOP("mov.b"),{ABS16OR8SRC, RD8, E}, { Hex6, HexA, Hex0, RD8,ABS16OR8SRC,
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IGNORE,IGNORE,IGNORE,E} EOP,
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SOP("mov.b"),{ABS8SRC, RD8, E}, { Hex2, RD8, ABS8SRC,IGNORE, E} EOP,
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SOP("mov.b"),{RS8, RDIND|B30, E}, { Hex6, Hex8, RDIND|B31, RS8, E} EOP,
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SOP("mov.b"),{RS8, DISPDST, E}, { Hex6, HexE, DISPREG|B31,
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RS8,DISPDST, IGNORE, IGNORE, IGNORE, E} EOP,
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SOP("mov.b"),{RS8, RDDEC|B31, E}, { Hex6, HexC, RDDEC|B31, RS8, E} EOP,
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SOP( "mov.b"),{RS8, ABS16OR8DST, E}, { Hex6, HexA, Hex8, RS8,
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ABS16OR8DST,IGNORE,IGNORE,IGNORE, E} EOP,
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SOP( "mov.b"),{RS8, ABS8DST, E}, { Hex3, RS8, ABS8DST,IGNORE, E} EOP,
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SOP( "mov.w"),{RS16|B30, RD16|B30, E},{ Hex0, HexD, RS16|B30,
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RD16|B30, E} EOP,
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SOP("mov.w"),{IMM16, RD16|B30, E}, { Hex7, Hex9, Hex0, RD16|B30,
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IMM16,IGNORE,IGNORE,IGNORE, E} EOP,
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SOP("mov.w"),{RSIND|B30,RD16|B30, E},{ Hex6, Hex9, RSIND|B30,
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RD16|B30, E} EOP,
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SOP("mov.w"),{DISPSRC,RD16|B30, E}, { Hex6, HexF, DISPREG|B30,
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RD16|B30, DISPSRC, IGNORE, IGNORE, IGNORE,E} EOP,
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SOP("mov.w"),{RSINC|B30, RD16|B30, E}, { Hex6, HexD, RSINC|B30,
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RD16|B30, E}EOP,
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SOP("mov.w"), {ABS16SRC, RD16|B30, E}, { Hex6, HexB, Hex0,
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RD16|B30,ABS16SRC,IGNORE,IGNORE,IGNORE, E} EOP,
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SOP("mov.w"), {RS16|B30, RDIND|B30, E},{ Hex6, Hex9, RDIND|B31,
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RS16|B30, E} EOP,
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SOP("mov.w"), {RS16|B30, DISPDST, E}, { Hex6, HexF, DISPREG|B31,
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RS16|B30,DISPDST, IGNORE,IGNORE,IGNORE,E} EOP,
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SOP("mov.w"), {RS16|B30, RDDEC|B30, E},{ Hex6, HexD, RDDEC|B31,
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RS16|B30, E} EOP,
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SOP("mov.w"), {RS16|B30, ABS16DST, E}, { Hex6, HexB, Hex8, RS16|B30,
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ABS16DST, IGNORE, IGNORE, IGNORE, E} EOP,
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SOP("movfpe"), {ABS16SRC, RD8, E}, { Hex6, HexA, Hex4, RD8,
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ABS16SRC,IGNORE,IGNORE,IGNORE, E} EOP,
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SOP("movtpe"), {RS8, ABS16DST, E}, { Hex6, HexA, HexC, RS8,
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ABS16DST,IGNORE,IGNORE,IGNORE,
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E} EOP,
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SOP("mulxu"), {RS8, RD16|B30, E}, { Hex5, Hex0, RS8, RD16|B30, E} EOP,
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SOP( "neg"), {RS8, E}, { Hex1, Hex7, Hex8, RS8, E} EOP,
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SOP( "nop"), {E}, { Hex0, Hex0, Hex0, Hex0,E} EOP,
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SOP( "not"), {RS8,E}, { Hex1, Hex7, Hex0, RS8,E} EOP,
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TWOOP("or", HexC, Hex1, Hex4),
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SOP( "orc"), {IMM8, CCR,E}, { Hex0, Hex4, IMM8,IGNORE,E} EOP,
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SOP( "pop"), {RS16|B30,E}, { Hex6, HexD, Hex7, RS16|B30,E} EOP,
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SOP( "push"), {RS16|B30,E}, { Hex6, HexD, HexF, RS16|B30,E} EOP,
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UNOP3( "rotl",Hex1, Hex2,Hex8),
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UNOP3( "rotr",Hex1, Hex3, Hex8),
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UNOP3( "rotxl",Hex1, Hex2, Hex0),
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UNOP3( "rotxr",Hex1, Hex3, Hex0),
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SOP("rte"), {E}, { Hex5, Hex6, Hex7, Hex0,E} EOP,
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SOP("rts"), {E}, { Hex5, Hex4, Hex7, Hex0,E} EOP,
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UNOP3( "shal", Hex1, Hex0, Hex8),
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UNOP3( "shar", Hex1, Hex1, Hex8),
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UNOP3( "shll", Hex1, Hex0, Hex0),
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UNOP3( "shlr", Hex1, Hex1, Hex0),
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SOP("sleep"), {E}, { Hex0, Hex1, Hex8, Hex0,E} EOP,
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SOP("stc"), {CCR, RD8,E}, { Hex0, Hex2, Hex0, RD8,E} EOP,
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SOP("sub.b"), {RS8,RD8,E}, { Hex1, Hex8, RS8, RD8,E} EOP,
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SOP("sub.w"), {RS16|B30, RD16|B30,E}, {Hex1, Hex9, RS16|B30,RD16|B30,E} EOP,
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SOP("subs"), {KBIT,RD16|B30,E}, { Hex1, HexB, KBIT, RD16|B30,E} EOP,
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TWOOP("subx",HexB, Hex1, HexE),
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TWOOP("xor", HexD, Hex1, Hex5),
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SOP("xorc"), {IMM8, CCR,E}, { Hex0, Hex5, IMM8,IGNORE,E} EOP,
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0
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};
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#else
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extern struct h8_opcode h8_opcodes[] ;
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#endif
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