f36f7c0bf8
single ICR MSR write. This is in contrast with the xAPIC mode, where we must read current ICR value, do bit fiddling and perform two 32-bit register writes. As a consequence, there is no need to disable interrupts around ICR value calculation and write. Note that typical users of ipi_raw() and ipi_vectored() take spinlock, which already disables interrupts. For them, the change removes unneeded CLI and POPFL/Q instructions. Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks |
||
---|---|---|
.. | ||
acpica | ||
bios | ||
cpufreq | ||
include | ||
iommu | ||
isa | ||
pci | ||
x86 | ||
xen |