f11c7f6305
The isci driver is for the integrated SAS controller in the Intel C600 (Patsburg) chipset. Source files in sys/dev/isci directory are FreeBSD-specific, and sys/dev/isci/scil subdirectory contains an OS-agnostic library (SCIL) published by Intel to control the SAS controller. This library is used primarily as-is in this driver, with some post-processing to better integrate into the kernel build environment. isci.4 and a README in the sys/dev/isci directory contain a few additional details. This driver is only built for amd64 and i386 targets. Sponsored by: Intel Reviewed by: scottl Approved by: scottl
139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SCIC_SDS_PCI_H_
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#define _SCIC_SDS_PCI_H_
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/**
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* @file
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*
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* @brief This file contains the prototypes/macros utilized in writing
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* out PCI data for the SCI core.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif // __cplusplus
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#include <dev/isci/scil/sci_types.h>
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#define PATSBURG_SMU_BAR 0
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#define PATSBURG_SCU_BAR 1
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#define PATSBURG_IO_SPACE_BAR0 2
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#define PATSBURG_IO_SPACE_BAR1 3
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#define SCIC_SDS_PCI_REVISION_A0 0
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#define SCIC_SDS_PCI_REVISION_A2 2
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#define SCIC_SDS_PCI_REVISION_B0 4
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#define SCIC_SDS_PCI_REVISION_C0 5
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#define SCIC_SDS_PCI_REVISION_C1 6
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enum SCU_CONTROLLER_PCI_REVISION_CODE
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{
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SCU_PBG_HBA_REV_A0 = SCIC_SDS_PCI_REVISION_A0,
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SCU_PBG_HBA_REV_A2 = SCIC_SDS_PCI_REVISION_A2,
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SCU_PBG_HBA_REV_B0 = SCIC_SDS_PCI_REVISION_B0,
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SCU_PBG_HBA_REV_C0 = SCIC_SDS_PCI_REVISION_C0,
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SCU_PBG_HBA_REV_C1 = SCIC_SDS_PCI_REVISION_C1
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};
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struct SCIC_SDS_CONTROLLER;
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void scic_sds_pci_bar_initialization(
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struct SCIC_SDS_CONTROLLER * this_controller
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);
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#if !defined(ENABLE_PCI_IO_SPACE_ACCESS) || defined(ARLINGTON_BUILD)
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#define scic_sds_pci_read_smu_dword scic_cb_pci_read_dword
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#define scic_sds_pci_write_smu_dword scic_cb_pci_write_dword
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#define scic_sds_pci_read_scu_dword scic_cb_pci_read_dword
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#define scic_sds_pci_write_scu_dword scic_cb_pci_write_dword
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#else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
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// These two registers form the Data/Index pair equivalent in the
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// SCU. They are only used for access registers in BAR 1, not BAR 0.
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#define SCU_MMR_ADDRESS_WINDOW_OFFSET 0xA0
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#define SCU_MMR_DATA_WINDOW_OFFSET 0xA4
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U32 scic_sds_pci_read_smu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address
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);
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void scic_sds_pci_write_smu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address,
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U32 write_value
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);
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U32 scic_sds_pci_read_scu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address
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);
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void scic_sds_pci_write_scu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address,
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U32 write_value
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);
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#endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
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#ifdef __cplusplus
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}
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#endif // __cplusplus
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#endif // _SCIC_SDS_PCI_H_
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