2dc8b759bd
will initialize the FIFO memory correctly on attach. Before that this values was intialized in only in at91_usart_bus_attach which is called after the uart(4) memory allocation happens. Approved by: re (kib) MFC after: 1 week
690 lines
18 KiB
C
690 lines
18 KiB
C
/*-
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* Copyright (c) 2005 M. Warner Losh
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* Copyright (c) 2005 Olivier Houchard
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_comconsole.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/cons.h>
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#include <sys/tty.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91_usartreg.h>
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#include <arm/at91/at91_pdcreg.h>
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#include <arm/at91/at91var.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK at91_master_clock
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#define USART_BUFFER_SIZE 128
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/*
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* High-level UART interface.
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*/
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struct at91_usart_rx {
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bus_addr_t pa;
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uint8_t buffer[USART_BUFFER_SIZE];
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bus_dmamap_t map;
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};
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struct at91_usart_softc {
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struct uart_softc base;
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bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
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bus_dmamap_t tx_map;
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uint32_t flags;
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#define HAS_TIMEOUT 1
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struct at91_usart_rx ping_pong[2];
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struct at91_usart_rx *ping;
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struct at91_usart_rx *pong;
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};
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#define RD4(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
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#define WR4(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
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#define SIGCHG(c, i, s, d) \
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do { \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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} \
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} while (0);
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#define BAUD2DIVISOR(b) \
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((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
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/*
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* Low-level UART interface.
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*/
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static int at91_usart_probe(struct uart_bas *bas);
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static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
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static void at91_usart_term(struct uart_bas *bas);
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static void at91_usart_putc(struct uart_bas *bas, int);
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static int at91_usart_rxready(struct uart_bas *bas);
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static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
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extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
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static int
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at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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uint32_t mr;
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/*
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* Assume 3-write RS-232 configuration.
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* XXX Not sure how uart will present the other modes to us, so
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* XXX they are unimplemented. maybe ioctl?
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*/
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mr = USART_MR_MODE_NORMAL;
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mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
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/*
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* Or in the databits requested
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*/
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if (databits < 9)
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mr &= ~USART_MR_MODE9;
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switch (databits) {
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case 5:
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mr |= USART_MR_CHRL_5BITS;
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break;
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case 6:
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mr |= USART_MR_CHRL_6BITS;
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break;
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case 7:
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mr |= USART_MR_CHRL_7BITS;
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break;
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case 8:
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mr |= USART_MR_CHRL_8BITS;
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break;
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case 9:
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mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
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break;
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default:
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return (EINVAL);
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}
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/*
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* Or in the parity
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*/
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switch (parity) {
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case UART_PARITY_NONE:
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mr |= USART_MR_PAR_NONE;
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break;
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case UART_PARITY_ODD:
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mr |= USART_MR_PAR_ODD;
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break;
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case UART_PARITY_EVEN:
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mr |= USART_MR_PAR_EVEN;
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break;
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case UART_PARITY_MARK:
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mr |= USART_MR_PAR_MARK;
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break;
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case UART_PARITY_SPACE:
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mr |= USART_MR_PAR_SPACE;
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break;
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default:
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return (EINVAL);
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}
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/*
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* Or in the stop bits. Note: The hardware supports 1.5 stop
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* bits in async mode, but there's no way to specify that
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* AFAICT. Instead, rely on the convention documented at
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* http://www.lammertbies.nl/comm/info/RS-232_specs.html which
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* states that 1.5 stop bits are used for 5 bit bytes and
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* 2 stop bits only for longer bytes.
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*/
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if (stopbits == 1)
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mr |= USART_MR_NBSTOP_1;
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else if (databits > 5)
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mr |= USART_MR_NBSTOP_2;
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else
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mr |= USART_MR_NBSTOP_1_5;
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/*
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* We want normal plumbing mode too, none of this fancy
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* loopback or echo mode.
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*/
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mr |= USART_MR_CHMODE_NORMAL;
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mr &= ~USART_MR_MSBF; /* lsb first */
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mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
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WR4(bas, USART_MR, mr);
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/*
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* Set the baud rate
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*/
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WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
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/* XXX Need to take possible synchronous mode into account */
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return (0);
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}
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static struct uart_ops at91_usart_ops = {
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.probe = at91_usart_probe,
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.init = at91_usart_init,
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.term = at91_usart_term,
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.putc = at91_usart_putc,
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.rxready = at91_usart_rxready,
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.getc = at91_usart_getc,
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};
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static int
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at91_usart_probe(struct uart_bas *bas)
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{
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/* We know that this is always here */
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return (0);
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}
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/*
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* Initialize this device for use as a console.
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*/
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static void
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at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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at91_usart_param(bas, baudrate, databits, stopbits, parity);
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/* Reset the rx and tx buffers and turn on rx and tx */
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WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
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WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
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WR4(bas, USART_IDR, 0xffffffff);
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}
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/*
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* Free resources now that we're no longer the console. This appears to
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* be never called, and I'm unsure quite what to do if I am called.
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*/
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static void
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at91_usart_term(struct uart_bas *bas)
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{
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/* XXX */
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}
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/*
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* Put a character of console output (so we do it here polling rather than
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* interrutp driven).
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*/
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static void
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at91_usart_putc(struct uart_bas *bas, int c)
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{
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while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
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continue;
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WR4(bas, USART_THR, c);
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}
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/*
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* Check for a character available.
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*/
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static int
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at91_usart_rxready(struct uart_bas *bas)
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{
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return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
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}
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/*
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* Block waiting for a character.
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*/
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static int
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at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
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{
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int c;
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while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
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continue;
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c = RD4(bas, USART_RHR);
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c &= 0xff;
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return (c);
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}
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static int at91_usart_bus_probe(struct uart_softc *sc);
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static int at91_usart_bus_attach(struct uart_softc *sc);
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static int at91_usart_bus_flush(struct uart_softc *, int);
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static int at91_usart_bus_getsig(struct uart_softc *);
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static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int at91_usart_bus_ipend(struct uart_softc *);
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static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
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static int at91_usart_bus_receive(struct uart_softc *);
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static int at91_usart_bus_setsig(struct uart_softc *, int);
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static int at91_usart_bus_transmit(struct uart_softc *);
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static kobj_method_t at91_usart_methods[] = {
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KOBJMETHOD(uart_probe, at91_usart_bus_probe),
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KOBJMETHOD(uart_attach, at91_usart_bus_attach),
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KOBJMETHOD(uart_flush, at91_usart_bus_flush),
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KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
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KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
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KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
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KOBJMETHOD(uart_param, at91_usart_bus_param),
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KOBJMETHOD(uart_receive, at91_usart_bus_receive),
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KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
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KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
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{ 0, 0 }
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};
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int
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at91_usart_bus_probe(struct uart_softc *sc)
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{
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sc->sc_txfifosz = USART_BUFFER_SIZE;
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sc->sc_rxfifosz = USART_BUFFER_SIZE;
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sc->sc_hwiflow = 0;
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return (0);
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}
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#ifndef SKYEYE_WORKAROUNDS
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static void
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at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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if (error != 0)
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return;
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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#endif
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static int
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at91_usart_bus_attach(struct uart_softc *sc)
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{
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#ifndef SKYEYE_WORKAROUNDS
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int err;
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int i;
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#endif
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uint32_t cr;
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struct at91_usart_softc *atsc;
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atsc = (struct at91_usart_softc *)sc;
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/*
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* See if we have a TIMEOUT bit. We disable all interrupts as
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* a side effect. Boot loaders may have enabled them. Since
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* a TIMEOUT interrupt can't happen without other setup, the
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* apparent race here can't actually happen.
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*/
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WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
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WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
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if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
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atsc->flags |= HAS_TIMEOUT;
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WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
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#ifndef SKYEYE_WORKAROUNDS
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/*
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* Allocate DMA tags and maps
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*/
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err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL,
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NULL, &atsc->dmatag);
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if (err != 0)
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goto errout;
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err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
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if (err != 0)
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goto errout;
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if (atsc->flags & HAS_TIMEOUT) {
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for (i = 0; i < 2; i++) {
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err = bus_dmamap_create(atsc->dmatag, 0,
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&atsc->ping_pong[i].map);
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if (err != 0)
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goto errout;
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err = bus_dmamap_load(atsc->dmatag,
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atsc->ping_pong[i].map,
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atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
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at91_getaddr, &atsc->ping_pong[i].pa, 0);
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if (err != 0)
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goto errout;
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bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
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BUS_DMASYNC_PREREAD);
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}
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atsc->ping = &atsc->ping_pong[0];
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atsc->pong = &atsc->ping_pong[1];
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}
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#endif
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/*
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* Prime the pump with the RX buffer. We use two 64 byte bounce
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* buffers here to avoid data overflow.
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*/
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/* Turn on rx and tx */
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cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
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WR4(&sc->sc_bas, USART_CR, cr);
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WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
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/*
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* Setup the PDC to receive data. We use the ping-pong buffers
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* so that we can more easily bounce between the two and so that
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* we get an interrupt 1/2 way through the software 'fifo' we have
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* to avoid overruns.
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*/
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if (atsc->flags & HAS_TIMEOUT) {
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WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
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WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
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WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
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WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
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WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
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/* Set the receive timeout to be 1.5 character times. */
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WR4(&sc->sc_bas, USART_RTOR, 12);
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WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
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WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
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USART_CSR_RXBUFF | USART_CSR_ENDRX);
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} else {
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WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
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}
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WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
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#ifndef SKYEYE_WORKAROUNDS
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errout:;
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// XXX bad
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return (err);
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#else
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return (0);
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#endif
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}
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static int
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at91_usart_bus_transmit(struct uart_softc *sc)
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{
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#ifndef SKYEYE_WORKAROUNDS
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bus_addr_t addr;
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#endif
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struct at91_usart_softc *atsc;
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atsc = (struct at91_usart_softc *)sc;
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#ifndef SKYEYE_WORKAROUNDS
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if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
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sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
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return (EAGAIN);
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bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
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#endif
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uart_lock(sc->sc_hwmtx);
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sc->sc_txbusy = 1;
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#ifndef SKYEYE_WORKAROUNDS
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/*
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* Setup the PDC to transfer the data and interrupt us when it
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* is done. We've already requested the interrupt.
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*/
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WR4(&sc->sc_bas, PDC_TPR, addr);
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WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
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WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
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WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
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uart_unlock(sc->sc_hwmtx);
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#else
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for (int i = 0; i < sc->sc_txdatasz; i++)
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at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
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/*
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* XXX: Gross hack : Skyeye doesn't raise an interrupt once the
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* transfer is done, so simulate it.
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*/
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WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
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#endif
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return (0);
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}
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static int
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at91_usart_bus_setsig(struct uart_softc *sc, int sig)
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{
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uint32_t new, old, cr;
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struct uart_bas *bas;
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do {
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old = sc->sc_hwsig;
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new = old;
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if (sig & SER_DDTR)
|
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SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
|
|
if (sig & SER_DRTS)
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
cr = 0;
|
|
if (new & SER_DTR)
|
|
cr |= USART_CR_DTREN;
|
|
else
|
|
cr |= USART_CR_DTRDIS;
|
|
if (new & SER_RTS)
|
|
cr |= USART_CR_RTSEN;
|
|
else
|
|
cr |= USART_CR_RTSDIS;
|
|
WR4(bas, USART_CR, cr);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
static int
|
|
at91_usart_bus_receive(struct uart_softc *sc)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
static int
|
|
at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
|
|
return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
|
|
parity));
|
|
}
|
|
|
|
static __inline void
|
|
at91_rx_put(struct uart_softc *sc, int key)
|
|
{
|
|
#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
|
|
int kdb_brk;
|
|
|
|
if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
|
|
if ((kdb_brk = kdb_alt_break(key, &sc->sc_altbrk)) != 0) {
|
|
switch (kdb_brk) {
|
|
case KDB_REQ_DEBUGGER:
|
|
kdb_enter(KDB_WHY_BREAK,
|
|
"Break sequence on console");
|
|
break;
|
|
case KDB_REQ_PANIC:
|
|
kdb_panic("Panic sequence on console");
|
|
break;
|
|
case KDB_REQ_REBOOT:
|
|
kdb_reboot();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
uart_rx_put(sc, key);
|
|
}
|
|
|
|
static int
|
|
at91_usart_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
int csr = RD4(&sc->sc_bas, USART_CSR);
|
|
int ipend = 0, i, len;
|
|
struct at91_usart_softc *atsc;
|
|
struct at91_usart_rx *p;
|
|
|
|
atsc = (struct at91_usart_softc *)sc;
|
|
if (csr & USART_CSR_ENDTX) {
|
|
bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
|
|
BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
|
|
}
|
|
uart_lock(sc->sc_hwmtx);
|
|
if (csr & USART_CSR_TXRDY) {
|
|
if (sc->sc_txbusy)
|
|
ipend |= SER_INT_TXIDLE;
|
|
WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
|
|
}
|
|
if (csr & USART_CSR_ENDTX) {
|
|
if (sc->sc_txbusy)
|
|
ipend |= SER_INT_TXIDLE;
|
|
WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
|
|
}
|
|
|
|
/*
|
|
* Due to the contraints of the DMA engine present in the
|
|
* atmel chip, I can't just say I have a rx interrupt pending
|
|
* and do all the work elsewhere. I need to look at the CSR
|
|
* bits right now and do things based on them to avoid races.
|
|
*/
|
|
if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
|
|
// Have a buffer overflow. Copy all data from both
|
|
// ping and pong. Insert overflow character. Reset
|
|
// ping and pong and re-enable the PDC to receive
|
|
// characters again.
|
|
bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
|
|
BUS_DMASYNC_POSTREAD);
|
|
bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
|
|
BUS_DMASYNC_POSTREAD);
|
|
for (i = 0; i < sc->sc_rxfifosz; i++)
|
|
at91_rx_put(sc, atsc->ping->buffer[i]);
|
|
for (i = 0; i < sc->sc_rxfifosz; i++)
|
|
at91_rx_put(sc, atsc->pong->buffer[i]);
|
|
uart_rx_put(sc, UART_STAT_OVERRUN);
|
|
csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
|
|
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
|
|
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
|
|
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
|
|
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
|
|
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
|
|
ipend |= SER_INT_RXREADY;
|
|
}
|
|
if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
|
|
// Shuffle data from 'ping' of ping pong buffer, but
|
|
// leave current 'pong' in place, as it has become the
|
|
// new 'ping'. We need to copy data and setup the old
|
|
// 'ping' as the new 'pong' when we're done.
|
|
bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
|
|
BUS_DMASYNC_POSTREAD);
|
|
for (i = 0; i < sc->sc_rxfifosz; i++)
|
|
at91_rx_put(sc, atsc->ping->buffer[i]);
|
|
p = atsc->ping;
|
|
atsc->ping = atsc->pong;
|
|
atsc->pong = p;
|
|
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
|
|
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
|
|
ipend |= SER_INT_RXREADY;
|
|
}
|
|
if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
|
|
// We have one partial buffer. We need to stop the
|
|
// PDC, get the number of characters left and from
|
|
// that compute number of valid characters. We then
|
|
// need to reset ping and pong and reenable the PDC.
|
|
// Not sure if there's a race here at fast baud rates
|
|
// we need to worry about.
|
|
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
|
|
bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
|
|
BUS_DMASYNC_POSTREAD);
|
|
len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
|
|
for (i = 0; i < len; i++)
|
|
at91_rx_put(sc, atsc->ping->buffer[i]);
|
|
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
|
|
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
|
|
WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
|
|
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
|
|
ipend |= SER_INT_RXREADY;
|
|
}
|
|
if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
|
|
// We have another charater in a device that doesn't support
|
|
// timeouts, so we do it one character at a time.
|
|
at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
|
|
ipend |= SER_INT_RXREADY;
|
|
}
|
|
|
|
if (csr & USART_CSR_RXBRK) {
|
|
unsigned int cr = USART_CR_RSTSTA;
|
|
|
|
ipend |= SER_INT_BREAK;
|
|
WR4(&sc->sc_bas, USART_CR, cr);
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (ipend);
|
|
}
|
|
static int
|
|
at91_usart_bus_flush(struct uart_softc *sc, int what)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
at91_usart_bus_getsig(struct uart_softc *sc)
|
|
{
|
|
uint32_t new, sig;
|
|
uint8_t csr;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
csr = RD4(&sc->sc_bas, USART_CSR);
|
|
sig = 0;
|
|
if (csr & USART_CSR_CTS)
|
|
sig |= SER_CTS;
|
|
if (csr & USART_CSR_DCD)
|
|
sig |= SER_DCD;
|
|
if (csr & USART_CSR_DSR)
|
|
sig |= SER_DSR;
|
|
if (csr & USART_CSR_RI)
|
|
sig |= SER_RI;
|
|
new = sig & ~SER_MASK_DELTA;
|
|
sc->sc_hwsig = new;
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (sig);
|
|
}
|
|
|
|
static int
|
|
at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
case UART_IOCTL_IFLOW:
|
|
case UART_IOCTL_OFLOW:
|
|
break;
|
|
case UART_IOCTL_BAUD:
|
|
WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
|
|
return (0);
|
|
}
|
|
return (EINVAL);
|
|
}
|
|
|
|
struct uart_class at91_usart_class = {
|
|
"at91_usart",
|
|
at91_usart_methods,
|
|
sizeof(struct at91_usart_softc),
|
|
.uc_ops = &at91_usart_ops,
|
|
.uc_range = 8
|
|
};
|