d5d4261f35
The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
715 lines
16 KiB
C
715 lines
16 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/rtprio.h>
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#include <sys/systm.h>
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#include <sys/interrupt.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/random.h>
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#include <sys/cons.h> /* cinit() */
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <sys/queue.h>
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#include <sys/smp.h>
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#include <sys/timetc.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/tlb.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/asm.h>
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#include <machine/pmap.h>
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#include <machine/trap.h>
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#include <machine/clock.h>
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#include <machine/fls64.h>
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#include <machine/intr_machdep.h>
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#include <machine/smp.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/pic.h>
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#include <mips/nlm/hal/uart.h>
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#include <mips/nlm/hal/mmu.h>
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#include <mips/nlm/hal/bridge.h>
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#include <mips/nlm/hal/cpucontrol.h>
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#include <mips/nlm/hal/cop2.h>
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#include <mips/nlm/clock.h>
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#include <mips/nlm/interrupt.h>
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#include <mips/nlm/board.h>
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#include <mips/nlm/xlp.h>
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#include <mips/nlm/msgring.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#endif
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/* 4KB static data aread to keep a copy of the bootload env until
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the dynamic kenv is setup */
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char boot1_env[4096];
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uint64_t xlp_cpu_frequency;
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uint64_t xlp_io_base = MIPS_PHYS_TO_DIRECT_UNCACHED(XLP_DEFAULT_IO_BASE);
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int xlp_ncores;
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int xlp_threads_per_core;
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uint32_t xlp_hw_thread_mask;
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int xlp_cpuid_to_hwtid[MAXCPU];
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int xlp_hwtid_to_cpuid[MAXCPU];
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uint64_t xlp_pic_base;
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static int xlp_mmuval;
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extern uint32_t _end;
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extern char XLPResetEntry[], XLPResetEntryEnd[];
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static void
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xlp_setup_core(void)
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{
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uint64_t reg;
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reg = nlm_mfcr(LSU_DEFEATURE);
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/* Enable Unaligned and L2HPE */
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reg |= (1 << 30) | (1 << 23);
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/*
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* Experimental : Enable SUE
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* Speculative Unmap Enable. Enable speculative L2 cache request for
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* unmapped access.
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*/
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reg |= (1ull << 31);
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/* Clear S1RCM - A0 errata */
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reg &= ~0xeull;
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nlm_mtcr(LSU_DEFEATURE, reg);
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reg = nlm_mfcr(SCHED_DEFEATURE);
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/* Experimental: Disable BRU accepting ALU ops - A0 errata */
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reg |= (1 << 24);
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nlm_mtcr(SCHED_DEFEATURE, reg);
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}
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static void
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xlp_setup_mmu(void)
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{
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uint32_t pagegrain;
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if (nlm_threadid() == 0) {
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nlm_setup_extended_pagemask(0);
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nlm_large_variable_tlb_en(1);
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nlm_extended_tlb_en(1);
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nlm_mmu_setup(0, 0, 0);
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}
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/* Enable no-read, no-exec, large-physical-address */
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pagegrain = mips_rd_pagegrain();
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pagegrain |= (1 << 31) | /* RIE */
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(1 << 30) | /* XIE */
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(1 << 29); /* ELPA */
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mips_wr_pagegrain(pagegrain);
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}
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static void
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xlp_parse_mmu_options(void)
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{
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uint64_t sysbase;
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uint32_t cpu_map = xlp_hw_thread_mask;
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uint32_t core0_thr_mask, core_thr_mask, cpu_rst_mask;
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int i, j, k;
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#ifdef SMP
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if (cpu_map == 0)
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cpu_map = 0xffffffff;
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#else /* Uniprocessor! */
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if (cpu_map == 0)
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cpu_map = 0x1;
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else if (cpu_map != 0x1) {
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printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
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"WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
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cpu_map = 0x1;
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}
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#endif
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xlp_ncores = 1;
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core0_thr_mask = cpu_map & 0xf;
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switch (core0_thr_mask) {
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case 1:
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xlp_threads_per_core = 1;
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xlp_mmuval = 0;
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break;
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case 3:
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xlp_threads_per_core = 2;
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xlp_mmuval = 2;
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break;
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case 0xf:
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xlp_threads_per_core = 4;
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xlp_mmuval = 3;
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break;
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default:
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goto unsupp;
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}
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/* Try to find the enabled cores from SYS block */
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sysbase = nlm_get_sys_regbase(0);
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cpu_rst_mask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET) & 0xff;
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/* XLP 416 does not report this correctly, fix */
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if (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_416)
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cpu_rst_mask = 0xe;
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/* Take out cores which do not exist on chip */
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for (i = 1; i < XLP_MAX_CORES; i++) {
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if ((cpu_rst_mask & (1 << i)) == 0)
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cpu_map &= ~(0xfu << (4 * i));
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}
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/* Verify other cores' CPU masks */
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for (i = 1; i < XLP_MAX_CORES; i++) {
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core_thr_mask = (cpu_map >> (4 * i)) & 0xf;
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if (core_thr_mask == 0)
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continue;
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if (core_thr_mask != core0_thr_mask)
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goto unsupp;
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xlp_ncores++;
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}
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xlp_hw_thread_mask = cpu_map;
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/* setup hardware processor id to cpu id mapping */
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for (i = 0; i< MAXCPU; i++)
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xlp_cpuid_to_hwtid[i] =
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xlp_hwtid_to_cpuid[i] = -1;
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for (i = 0, k = 0; i < XLP_MAX_CORES; i++) {
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if (((cpu_map >> (i * 4)) & 0xf) == 0)
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continue;
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for (j = 0; j < xlp_threads_per_core; j++) {
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xlp_cpuid_to_hwtid[k] = i * 4 + j;
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xlp_hwtid_to_cpuid[i * 4 + j] = k;
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k++;
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}
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}
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return;
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unsupp:
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printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
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"\tcore0 thread mask [%lx], boot cpu mask [%lx].\n",
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(u_long)core0_thr_mask, (u_long)cpu_map);
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panic("Invalid CPU mask - halting.\n");
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return;
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}
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/* Parse cmd line args as env - copied from ar71xx */
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static void
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xlp_parse_bootargs(char *cmdline)
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{
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char *n, *v;
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while ((v = strsep(&cmdline, " \n")) != NULL) {
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if (*v == '\0')
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continue;
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if (*v == '-') {
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while (*v != '\0') {
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v++;
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switch (*v) {
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case 'a': boothowto |= RB_ASKNAME; break;
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case 'd': boothowto |= RB_KDB; break;
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case 'g': boothowto |= RB_GDB; break;
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case 's': boothowto |= RB_SINGLE; break;
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case 'v': boothowto |= RB_VERBOSE; break;
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}
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}
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} else {
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n = strsep(&v, "=");
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if (v == NULL)
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setenv(n, "1");
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else
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setenv(n, v);
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}
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}
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}
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#ifdef FDT
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static void
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xlp_bootargs_init(__register_t arg)
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{
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char buf[2048]; /* early stack is big enough */
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void *dtbp;
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phandle_t chosen;
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ihandle_t mask;
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dtbp = (void *)(intptr_t)arg;
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#if defined(FDT_DTB_STATIC)
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/*
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* In case the device tree blob was not passed as argument try
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* to use the statically embedded one.
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*/
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if (dtbp == NULL)
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dtbp = &fdt_static_dtb;
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#endif
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if (OF_install(OFW_FDT, 0) == FALSE)
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while (1);
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if (OF_init((void *)dtbp) != 0)
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while (1);
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if (fdt_immr_addr(xlp_io_base) != 0)
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while (1);
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OF_interpret("perform-fixup", 0);
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chosen = OF_finddevice("/chosen");
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if (OF_getprop(chosen, "cpumask", &mask, sizeof(mask)) != -1) {
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xlp_hw_thread_mask = mask;
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}
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if (OF_getprop(chosen, "bootargs", buf, sizeof(buf)) != -1)
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xlp_parse_bootargs(buf);
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}
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#else
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/*
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* arg is a pointer to the environment block, the format of the block is
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* a=xyz\0b=pqr\0\0
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*/
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static void
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xlp_bootargs_init(__register_t arg)
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{
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char buf[2048]; /* early stack is big enough */
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char *p, *v, *n;
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uint32_t mask;
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/*
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* provide backward compat for passing cpu mask as arg
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*/
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if (arg & 1) {
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xlp_hw_thread_mask = arg;
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return;
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}
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p = (void *)(intptr_t)arg;
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while (*p != '\0') {
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strlcpy(buf, p, sizeof(buf));
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v = buf;
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n = strsep(&v, "=");
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if (v == NULL)
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setenv(n, "1");
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else
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setenv(n, v);
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p += strlen(p) + 1;
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}
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/* CPU mask can be passed thru env */
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if (getenv_uint("cpumask", &mask) != 0)
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xlp_hw_thread_mask = mask;
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/* command line argument */
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v = getenv("bootargs");
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if (v != NULL) {
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strlcpy(buf, v, sizeof(buf));
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xlp_parse_bootargs(buf);
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freeenv(v);
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}
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}
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#endif
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static void
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mips_init(void)
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{
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init_param1();
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init_param2(physmem);
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mips_cpu_init();
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cpuinfo.cache_coherent_dma = TRUE;
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pmap_bootstrap();
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mips_proc0_init();
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mutex_init();
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#ifdef DDB
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kdb_init();
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if (boothowto & RB_KDB) {
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kdb_enter("Boot flags requested debugger", NULL);
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}
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#endif
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}
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unsigned int
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platform_get_timecount(struct timecounter *tc __unused)
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{
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uint64_t count = nlm_pic_read_timer(xlp_pic_base, PIC_CLOCK_TIMER);
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return (unsigned int)~count;
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}
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static void
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xlp_pic_init(void)
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{
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struct timecounter pic_timecounter = {
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platform_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0U, /* counter_mask */
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XLP_IO_CLK, /* frequency */
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"XLRPIC", /* name */
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2000, /* quality (adjusted in code) */
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};
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int i;
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int maxirt;
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xlp_pic_base = nlm_get_pic_regbase(0); /* TOOD: Add other nodes */
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maxirt = nlm_read_reg(nlm_get_pic_pcibase(nlm_nodeid()),
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XLP_PCI_DEVINFO_REG0);
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printf("Initializing PIC...@%jx %d IRTs\n", (uintmax_t)xlp_pic_base,
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maxirt);
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/* Bind all PIC irqs to cpu 0 */
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for (i = 0; i < maxirt; i++)
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nlm_pic_write_irt(xlp_pic_base, i, 0, 0, 1, 0,
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1, 0, 0x1);
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nlm_pic_set_timer(xlp_pic_base, PIC_CLOCK_TIMER, ~0ULL, 0, 0);
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platform_timecounter = &pic_timecounter;
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}
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#if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */
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#ifdef XLP_SIM
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#define XLP_MEM_LIM 0x200000000ULL
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#else
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#define XLP_MEM_LIM 0x10000000000ULL
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#endif
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#else
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#define XLP_MEM_LIM 0xfffff000UL
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#endif
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static void
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xlp_mem_init(void)
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{
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uint64_t bridgebase = nlm_get_bridge_regbase(0); /* TOOD: Add other nodes */
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vm_size_t physsz = 0;
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uint64_t base, lim, val;
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int i, j;
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for (i = 0, j = 0; i < 8; i++) {
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val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
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base = ((val >> 12) & 0xfffff) << 20;
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val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
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lim = ((val >> 12) & 0xfffff) << 20;
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/* BAR not enabled */
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if (lim == 0)
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continue;
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/* first bar, start a bit after end */
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if (base == 0) {
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base = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(&_end);
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base = round_page(base) + 0x20000; /* round up */
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/* TODO : hack to avoid uboot packet mem, network
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* interface will write here if not reset correctly
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* by u-boot */
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lim = 0x0c000000;
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}
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if (base >= XLP_MEM_LIM) {
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printf("Mem [%d]: Ignore %#jx - %#jx\n", i,
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(intmax_t)base, (intmax_t)lim);
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continue;
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}
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if (lim > XLP_MEM_LIM) {
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printf("Mem [%d]: Restrict %#jx -> %#jx\n", i,
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(intmax_t)lim, (intmax_t)XLP_MEM_LIM);
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lim = XLP_MEM_LIM;
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}
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if (lim <= base) {
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printf("Mem[%d]: Malformed %#jx -> %#jx\n", i,
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(intmax_t)base, (intmax_t)lim);
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continue;
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}
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/*
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* Exclude reset entry memory range 0x1fc00000 - 0x20000000
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* from free memory
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*/
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if (base < 0x20000000 && lim > 0x1fc00000) {
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uint64_t base0, lim0, base1, lim1;
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base0 = base;
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lim0 = 0x1fc00000;
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base1 = 0x20000000;
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lim1 = lim;
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if (lim0 > base0) {
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phys_avail[j++] = (vm_paddr_t)base0;
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phys_avail[j++] = (vm_paddr_t)lim0;
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physsz += lim0 - base0;
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printf("Mem[%d]: %#jx - %#jx (excl reset)\n", i,
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(intmax_t)base0, (intmax_t)lim0);
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}
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if (lim1 > base1) {
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phys_avail[j++] = (vm_paddr_t)base1;
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phys_avail[j++] = (vm_paddr_t)lim1;
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physsz += lim1 - base1;
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printf("Mem[%d]: %#jx - %#jx (excl reset)\n", i,
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(intmax_t)base1, (intmax_t)lim1);
|
|
}
|
|
} else {
|
|
phys_avail[j++] = (vm_paddr_t)base;
|
|
phys_avail[j++] = (vm_paddr_t)lim;
|
|
physsz += lim - base;
|
|
printf("Mem[%d]: %#jx - %#jx\n", i,
|
|
(intmax_t)base, (intmax_t)lim);
|
|
}
|
|
|
|
}
|
|
|
|
/* setup final entry with 0 */
|
|
phys_avail[j] = phys_avail[j + 1] = 0;
|
|
|
|
/* copy phys_avail to dump_avail */
|
|
for (i = 0; i <= j + 1; i++)
|
|
dump_avail[i] = phys_avail[i];
|
|
|
|
realmem = physmem = btoc(physsz);
|
|
}
|
|
|
|
void
|
|
platform_start(__register_t a0 __unused,
|
|
__register_t a1 __unused,
|
|
__register_t a2 __unused,
|
|
__register_t a3 __unused)
|
|
{
|
|
|
|
/* Initialize pcpu stuff */
|
|
mips_pcpu0_init();
|
|
|
|
/* initialize console so that we have printf */
|
|
boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
|
|
|
|
init_static_kenv(boot1_env, sizeof(boot1_env));
|
|
xlp_bootargs_init(a0);
|
|
|
|
/* clockrate used by delay, so initialize it here */
|
|
xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0);
|
|
cpu_clock = xlp_cpu_frequency / 1000000;
|
|
mips_timer_early_init(xlp_cpu_frequency);
|
|
|
|
/* Init console please */
|
|
cninit();
|
|
|
|
/* Early core init and fixes for errata */
|
|
xlp_setup_core();
|
|
|
|
xlp_parse_mmu_options();
|
|
xlp_mem_init();
|
|
|
|
bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC,
|
|
XLPResetEntryEnd - XLPResetEntry);
|
|
#ifdef SMP
|
|
/*
|
|
* We will enable the other threads in core 0 here
|
|
* so that the TLB and cache info is correct when
|
|
* mips_init runs
|
|
*/
|
|
xlp_enable_threads(xlp_mmuval);
|
|
#endif
|
|
/* setup for the startup core */
|
|
xlp_setup_mmu();
|
|
|
|
/* Read/Guess/setup board information */
|
|
nlm_board_info_setup();
|
|
|
|
/* MIPS generic init */
|
|
mips_init();
|
|
|
|
/*
|
|
* XLP specific post initialization
|
|
* initialize other on chip stuff
|
|
*/
|
|
xlp_pic_init();
|
|
|
|
mips_timer_init_params(xlp_cpu_frequency, 0);
|
|
}
|
|
|
|
void
|
|
platform_cpu_init()
|
|
{
|
|
}
|
|
|
|
void
|
|
platform_reset(void)
|
|
{
|
|
uint64_t sysbase = nlm_get_sys_regbase(0);
|
|
|
|
nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
|
|
for( ; ; )
|
|
__asm __volatile("wait");
|
|
}
|
|
|
|
#ifdef SMP
|
|
/*
|
|
* XLP threads are started simultaneously when we enable threads, this will
|
|
* ensure that the threads are blocked in platform_init_ap, until they are
|
|
* ready to proceed to smp_init_secondary()
|
|
*/
|
|
static volatile int thr_unblock[4];
|
|
|
|
int
|
|
platform_start_ap(int cpuid)
|
|
{
|
|
uint32_t coremask, val;
|
|
uint64_t sysbase = nlm_get_sys_regbase(0);
|
|
int hwtid = xlp_cpuid_to_hwtid[cpuid];
|
|
int core, thr;
|
|
|
|
core = hwtid / 4;
|
|
thr = hwtid % 4;
|
|
if (thr == 0) {
|
|
/* First thread in core, do core wake up */
|
|
coremask = 1u << core;
|
|
|
|
/* Enable core clock */
|
|
val = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
|
|
val &= ~coremask;
|
|
nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, val);
|
|
|
|
/* Remove CPU Reset */
|
|
val = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
|
|
val &= ~coremask & 0xff;
|
|
nlm_write_sys_reg(sysbase, SYS_CPU_RESET, val);
|
|
|
|
if (bootverbose)
|
|
printf("Waking up core %d ...", core);
|
|
|
|
/* Poll for CPU to mark itself coherent */
|
|
do {
|
|
val = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
|
|
} while ((val & coremask) != 0);
|
|
if (bootverbose)
|
|
printf("Done\n");
|
|
} else {
|
|
/* otherwise release the threads stuck in platform_init_ap */
|
|
thr_unblock[thr] = 1;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
platform_init_ap(int cpuid)
|
|
{
|
|
uint32_t stat;
|
|
int thr;
|
|
|
|
/* The first thread has to setup the MMU and enable other threads */
|
|
thr = nlm_threadid();
|
|
if (thr == 0) {
|
|
xlp_setup_core();
|
|
xlp_enable_threads(xlp_mmuval);
|
|
} else {
|
|
/*
|
|
* FIXME busy wait here eats too many cycles, especially
|
|
* in the core 0 while bootup
|
|
*/
|
|
while (thr_unblock[thr] == 0)
|
|
__asm__ __volatile__ ("nop;nop;nop;nop");
|
|
thr_unblock[thr] = 0;
|
|
}
|
|
|
|
xlp_setup_mmu();
|
|
stat = mips_rd_status();
|
|
KASSERT((stat & MIPS_SR_INT_IE) == 0,
|
|
("Interrupts enabled in %s!", __func__));
|
|
stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
|
|
mips_wr_status(stat);
|
|
|
|
nlm_write_c0_eimr(0ull);
|
|
xlp_enable_irq(IRQ_IPI);
|
|
xlp_enable_irq(IRQ_TIMER);
|
|
xlp_enable_irq(IRQ_MSGRING);
|
|
|
|
return;
|
|
}
|
|
|
|
int
|
|
platform_ipi_intrnum(void)
|
|
{
|
|
|
|
return (IRQ_IPI);
|
|
}
|
|
|
|
void
|
|
platform_ipi_send(int cpuid)
|
|
{
|
|
|
|
nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid],
|
|
platform_ipi_intrnum(), 0);
|
|
}
|
|
|
|
void
|
|
platform_ipi_clear(void)
|
|
{
|
|
}
|
|
|
|
int
|
|
platform_processor_id(void)
|
|
{
|
|
|
|
return (xlp_hwtid_to_cpuid[nlm_cpuid()]);
|
|
}
|
|
|
|
void
|
|
platform_cpu_mask(cpuset_t *mask)
|
|
{
|
|
int i, s;
|
|
|
|
CPU_ZERO(mask);
|
|
s = xlp_ncores * xlp_threads_per_core;
|
|
for (i = 0; i < s; i++)
|
|
CPU_SET(i, mask);
|
|
}
|
|
|
|
struct cpu_group *
|
|
platform_smp_topo()
|
|
{
|
|
|
|
return (smp_topo_2level(CG_SHARE_L2, xlp_ncores, CG_SHARE_L1,
|
|
xlp_threads_per_core, CG_FLAG_THREAD));
|
|
}
|
|
#endif
|