1104 lines
31 KiB
C
1104 lines
31 KiB
C
/*-
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* Copyright (c) 1990 William Jolitz.
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)npx.c 7.2 (Berkeley) 5/12/91
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include "opt_isa.h"
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#include "opt_npx.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#ifdef NPX_DEBUG
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#include <sys/syslog.h>
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#endif
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#include <sys/signalvar.h>
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#include <machine/asmacros.h>
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#include <machine/cputypes.h>
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#include <machine/frame.h>
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#include <machine/md_var.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/resource.h>
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#include <machine/specialreg.h>
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#include <machine/segments.h>
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#include <machine/ucontext.h>
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#include <machine/intr_machdep.h>
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#ifdef XEN
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#include <machine/xen/xen-os.h>
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#include <xen/hypervisor.h>
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#endif
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#ifdef DEV_ISA
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#include <isa/isavar.h>
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#endif
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#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
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#define CPU_ENABLE_SSE
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#endif
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/*
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* 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
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*/
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#if defined(__GNUCLIKE_ASM) && !defined(lint)
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#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
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#define fnclex() __asm("fnclex")
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#define fninit() __asm("fninit")
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#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
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#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
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#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
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#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
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#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
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#ifdef CPU_ENABLE_SSE
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#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
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#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
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#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
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#endif
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#ifdef XEN
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#define start_emulating() (HYPERVISOR_fpu_taskswitch(1))
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#define stop_emulating() (HYPERVISOR_fpu_taskswitch(0))
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#else
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#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
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: : "n" (CR0_TS) : "ax")
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#define stop_emulating() __asm("clts")
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#endif
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#else /* !(__GNUCLIKE_ASM && !lint) */
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void fldcw(caddr_t addr);
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void fnclex(void);
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void fninit(void);
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void fnsave(caddr_t addr);
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void fnstcw(caddr_t addr);
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void fnstsw(caddr_t addr);
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void fp_divide_by_0(void);
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void frstor(caddr_t addr);
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#ifdef CPU_ENABLE_SSE
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void fxsave(caddr_t addr);
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void fxrstor(caddr_t addr);
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#endif
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void start_emulating(void);
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void stop_emulating(void);
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#endif /* __GNUCLIKE_ASM && !lint */
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#ifdef CPU_ENABLE_SSE
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#define GET_FPU_CW(thread) \
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(cpu_fxsr ? \
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(thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
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(thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
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#define GET_FPU_SW(thread) \
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(cpu_fxsr ? \
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(thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
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(thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
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#define SET_FPU_CW(savefpu, value) do { \
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if (cpu_fxsr) \
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(savefpu)->sv_xmm.sv_env.en_cw = (value); \
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else \
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(savefpu)->sv_87.sv_env.en_cw = (value); \
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} while (0)
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#else /* CPU_ENABLE_SSE */
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#define GET_FPU_CW(thread) \
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(thread->td_pcb->pcb_save->sv_87.sv_env.en_cw)
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#define GET_FPU_SW(thread) \
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(thread->td_pcb->pcb_save->sv_87.sv_env.en_sw)
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#define SET_FPU_CW(savefpu, value) \
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(savefpu)->sv_87.sv_env.en_cw = (value)
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#endif /* CPU_ENABLE_SSE */
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typedef u_char bool_t;
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#ifdef CPU_ENABLE_SSE
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static void fpu_clean_state(void);
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#endif
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static void fpusave(union savefpu *);
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static void fpurstor(union savefpu *);
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static int npx_attach(device_t dev);
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static void npx_identify(driver_t *driver, device_t parent);
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static int npx_probe(device_t dev);
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int hw_float;
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SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
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&hw_float, 0, "Floating point instructions executed in hardware");
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static volatile u_int npx_traps_while_probing;
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static union savefpu npx_initialstate;
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alias_for_inthand_t probetrap;
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__asm(" \n\
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.text \n\
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.p2align 2,0x90 \n\
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.type " __XSTRING(CNAME(probetrap)) ",@function \n\
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" __XSTRING(CNAME(probetrap)) ": \n\
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ss \n\
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incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
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fnclex \n\
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iret \n\
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");
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/*
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* Identify routine. Create a connection point on our parent for probing.
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*/
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static void
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npx_identify(driver, parent)
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driver_t *driver;
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device_t parent;
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{
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device_t child;
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child = BUS_ADD_CHILD(parent, 0, "npx", 0);
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if (child == NULL)
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panic("npx_identify");
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}
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/*
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* Probe routine. Set flags to tell npxattach() what to do. Set up an
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* interrupt handler if npx needs to use interrupts.
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*/
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static int
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npx_probe(device_t dev)
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{
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struct gate_descriptor save_idt_npxtrap;
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u_short control, status;
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device_set_desc(dev, "math processor");
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/*
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* Modern CPUs all have an FPU that uses the INT16 interface
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* and provide a simple way to verify that, so handle the
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* common case right away.
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*/
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if (cpu_feature & CPUID_FPU) {
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hw_float = 1;
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device_quiet(dev);
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return (0);
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}
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save_idt_npxtrap = idt[IDT_MF];
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setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
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GSEL(GCODE_SEL, SEL_KPL));
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/*
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* Don't trap while we're probing.
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*/
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stop_emulating();
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/*
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* Finish resetting the coprocessor, if any. If there is an error
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* pending, then we may get a bogus IRQ13, but npx_intr() will handle
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* it OK. Bogus halts have never been observed, but we enabled
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* IRQ13 and cleared the BUSY# latch early to handle them anyway.
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*/
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fninit();
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/*
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* Don't use fwait here because it might hang.
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* Don't use fnop here because it usually hangs if there is no FPU.
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*/
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DELAY(1000); /* wait for any IRQ13 */
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#ifdef DIAGNOSTIC
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if (npx_traps_while_probing != 0)
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printf("fninit caused %u bogus npx trap(s)\n",
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npx_traps_while_probing);
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#endif
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/*
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* Check for a status of mostly zero.
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*/
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status = 0x5a5a;
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fnstsw(&status);
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if ((status & 0xb8ff) == 0) {
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/*
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* Good, now check for a proper control word.
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*/
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control = 0x5a5a;
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fnstcw(&control);
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if ((control & 0x1f3f) == 0x033f) {
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/*
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* We have an npx, now divide by 0 to see if exception
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* 16 works.
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*/
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control &= ~(1 << 2); /* enable divide by 0 trap */
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fldcw(&control);
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#ifdef FPU_ERROR_BROKEN
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/*
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* FPU error signal doesn't work on some CPU
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* accelerator board.
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*/
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hw_float = 1;
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return (0);
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#endif
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npx_traps_while_probing = 0;
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fp_divide_by_0();
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if (npx_traps_while_probing != 0) {
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/*
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* Good, exception 16 works.
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*/
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hw_float = 1;
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goto cleanup;
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}
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device_printf(dev,
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"FPU does not use exception 16 for error reporting\n");
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goto cleanup;
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}
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}
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/*
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* Probe failed. Floating point simply won't work.
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* Notify user and disable FPU/MMX/SSE instruction execution.
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*/
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device_printf(dev, "WARNING: no FPU!\n");
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__asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
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"n" (CR0_EM | CR0_MP) : "ax");
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cleanup:
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idt[IDT_MF] = save_idt_npxtrap;
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return (hw_float ? 0 : ENXIO);
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}
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/*
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* Attach routine - announce which it is, and wire into system
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*/
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static int
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npx_attach(device_t dev)
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{
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npxinit();
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critical_enter();
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stop_emulating();
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fpusave(&npx_initialstate);
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start_emulating();
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#ifdef CPU_ENABLE_SSE
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if (cpu_fxsr) {
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if (npx_initialstate.sv_xmm.sv_env.en_mxcsr_mask)
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cpu_mxcsr_mask =
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npx_initialstate.sv_xmm.sv_env.en_mxcsr_mask;
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else
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cpu_mxcsr_mask = 0xFFBF;
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bzero(npx_initialstate.sv_xmm.sv_fp,
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sizeof(npx_initialstate.sv_xmm.sv_fp));
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bzero(npx_initialstate.sv_xmm.sv_xmm,
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sizeof(npx_initialstate.sv_xmm.sv_xmm));
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/* XXX might need even more zeroing. */
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} else
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#endif
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bzero(npx_initialstate.sv_87.sv_ac,
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sizeof(npx_initialstate.sv_87.sv_ac));
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critical_exit();
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return (0);
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}
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/*
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* Initialize floating point unit.
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*/
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void
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npxinit(void)
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{
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static union savefpu dummy;
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register_t savecrit;
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u_short control;
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if (!hw_float)
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return;
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/*
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* fninit has the same h/w bugs as fnsave. Use the detoxified
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* fnsave to throw away any junk in the fpu. npxsave() initializes
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* the fpu and sets fpcurthread = NULL as important side effects.
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*
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* It is too early for critical_enter() to work on AP.
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*/
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savecrit = intr_disable();
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npxsave(&dummy);
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stop_emulating();
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#ifdef CPU_ENABLE_SSE
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/* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
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if (cpu_fxsr)
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fninit();
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#endif
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control = __INITIAL_NPXCW__;
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fldcw(&control);
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start_emulating();
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intr_restore(savecrit);
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}
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/*
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* Free coprocessor (if we have it).
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*/
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void
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npxexit(td)
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struct thread *td;
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{
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critical_enter();
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if (curthread == PCPU_GET(fpcurthread))
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npxsave(PCPU_GET(curpcb)->pcb_save);
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critical_exit();
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#ifdef NPX_DEBUG
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if (hw_float) {
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u_int masked_exceptions;
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masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
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/*
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* Log exceptions that would have trapped with the old
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* control word (overflow, divide by 0, and invalid operand).
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*/
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if (masked_exceptions & 0x0d)
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log(LOG_ERR,
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"pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
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td->td_proc->p_pid, td->td_proc->p_comm,
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masked_exceptions);
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}
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#endif
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}
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int
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npxformat()
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{
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if (!hw_float)
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return (_MC_FPFMT_NODEV);
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#ifdef CPU_ENABLE_SSE
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if (cpu_fxsr)
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return (_MC_FPFMT_XMM);
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#endif
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return (_MC_FPFMT_387);
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}
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/*
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* The following mechanism is used to ensure that the FPE_... value
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* that is passed as a trapcode to the signal handler of the user
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* process does not have more than one bit set.
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*
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* Multiple bits may be set if the user process modifies the control
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* word while a status word bit is already set. While this is a sign
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* of bad coding, we have no choise than to narrow them down to one
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* bit, since we must not send a trapcode that is not exactly one of
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* the FPE_ macros.
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*
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* The mechanism has a static table with 127 entries. Each combination
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* of the 7 FPU status word exception bits directly translates to a
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* position in this table, where a single FPE_... value is stored.
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* This FPE_... value stored there is considered the "most important"
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* of the exception bits and will be sent as the signal code. The
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* precedence of the bits is based upon Intel Document "Numerical
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* Applications", Chapter "Special Computational Situations".
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*
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* The macro to choose one of these values does these steps: 1) Throw
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* away status word bits that cannot be masked. 2) Throw away the bits
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* currently masked in the control word, assuming the user isn't
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* interested in them anymore. 3) Reinsert status word bit 7 (stack
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* fault) if it is set, which cannot be masked but must be presered.
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* 4) Use the remaining bits to point into the trapcode table.
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*
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* The 6 maskable bits in order of their preference, as stated in the
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* above referenced Intel manual:
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* 1 Invalid operation (FP_X_INV)
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* 1a Stack underflow
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* 1b Stack overflow
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* 1c Operand of unsupported format
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* 1d SNaN operand.
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* 2 QNaN operand (not an exception, irrelavant here)
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* 3 Any other invalid-operation not mentioned above or zero divide
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* (FP_X_INV, FP_X_DZ)
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* 4 Denormal operand (FP_X_DNML)
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* 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
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* 6 Inexact result (FP_X_IMP)
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*/
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static char fpetable[128] = {
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0,
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FPE_FLTINV, /* 1 - INV */
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FPE_FLTUND, /* 2 - DNML */
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FPE_FLTINV, /* 3 - INV | DNML */
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FPE_FLTDIV, /* 4 - DZ */
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FPE_FLTINV, /* 5 - INV | DZ */
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FPE_FLTDIV, /* 6 - DNML | DZ */
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FPE_FLTINV, /* 7 - INV | DNML | DZ */
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FPE_FLTOVF, /* 8 - OFL */
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FPE_FLTINV, /* 9 - INV | OFL */
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FPE_FLTUND, /* A - DNML | OFL */
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FPE_FLTINV, /* B - INV | DNML | OFL */
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FPE_FLTDIV, /* C - DZ | OFL */
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FPE_FLTINV, /* D - INV | DZ | OFL */
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FPE_FLTDIV, /* E - DNML | DZ | OFL */
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FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
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FPE_FLTUND, /* 10 - UFL */
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FPE_FLTINV, /* 11 - INV | UFL */
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FPE_FLTUND, /* 12 - DNML | UFL */
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FPE_FLTINV, /* 13 - INV | DNML | UFL */
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FPE_FLTDIV, /* 14 - DZ | UFL */
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FPE_FLTINV, /* 15 - INV | DZ | UFL */
|
|
FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
|
|
FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
|
|
FPE_FLTOVF, /* 18 - OFL | UFL */
|
|
FPE_FLTINV, /* 19 - INV | OFL | UFL */
|
|
FPE_FLTUND, /* 1A - DNML | OFL | UFL */
|
|
FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
|
|
FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
|
|
FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
|
|
FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
|
|
FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
|
|
FPE_FLTRES, /* 20 - IMP */
|
|
FPE_FLTINV, /* 21 - INV | IMP */
|
|
FPE_FLTUND, /* 22 - DNML | IMP */
|
|
FPE_FLTINV, /* 23 - INV | DNML | IMP */
|
|
FPE_FLTDIV, /* 24 - DZ | IMP */
|
|
FPE_FLTINV, /* 25 - INV | DZ | IMP */
|
|
FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
|
|
FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
|
|
FPE_FLTOVF, /* 28 - OFL | IMP */
|
|
FPE_FLTINV, /* 29 - INV | OFL | IMP */
|
|
FPE_FLTUND, /* 2A - DNML | OFL | IMP */
|
|
FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
|
|
FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
|
|
FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
|
|
FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
|
|
FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
|
|
FPE_FLTUND, /* 30 - UFL | IMP */
|
|
FPE_FLTINV, /* 31 - INV | UFL | IMP */
|
|
FPE_FLTUND, /* 32 - DNML | UFL | IMP */
|
|
FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
|
|
FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
|
|
FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
|
|
FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
|
|
FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
|
|
FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
|
|
FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
|
|
FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
|
|
FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
|
|
FPE_FLTSUB, /* 40 - STK */
|
|
FPE_FLTSUB, /* 41 - INV | STK */
|
|
FPE_FLTUND, /* 42 - DNML | STK */
|
|
FPE_FLTSUB, /* 43 - INV | DNML | STK */
|
|
FPE_FLTDIV, /* 44 - DZ | STK */
|
|
FPE_FLTSUB, /* 45 - INV | DZ | STK */
|
|
FPE_FLTDIV, /* 46 - DNML | DZ | STK */
|
|
FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
|
|
FPE_FLTOVF, /* 48 - OFL | STK */
|
|
FPE_FLTSUB, /* 49 - INV | OFL | STK */
|
|
FPE_FLTUND, /* 4A - DNML | OFL | STK */
|
|
FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
|
|
FPE_FLTDIV, /* 4C - DZ | OFL | STK */
|
|
FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
|
|
FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
|
|
FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
|
|
FPE_FLTUND, /* 50 - UFL | STK */
|
|
FPE_FLTSUB, /* 51 - INV | UFL | STK */
|
|
FPE_FLTUND, /* 52 - DNML | UFL | STK */
|
|
FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
|
|
FPE_FLTDIV, /* 54 - DZ | UFL | STK */
|
|
FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
|
|
FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
|
|
FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
|
|
FPE_FLTOVF, /* 58 - OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
|
|
FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
|
|
FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
|
|
FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
|
|
FPE_FLTRES, /* 60 - IMP | STK */
|
|
FPE_FLTSUB, /* 61 - INV | IMP | STK */
|
|
FPE_FLTUND, /* 62 - DNML | IMP | STK */
|
|
FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
|
|
FPE_FLTDIV, /* 64 - DZ | IMP | STK */
|
|
FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
|
|
FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
|
|
FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
|
|
FPE_FLTOVF, /* 68 - OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
|
|
FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
|
|
FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
|
|
FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
|
|
FPE_FLTUND, /* 70 - UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
|
|
FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
|
|
FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
|
|
FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
|
|
};
|
|
|
|
/*
|
|
* Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
|
|
*
|
|
* Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
|
|
* depend on longjmp() restoring a usable state. Restoring the state
|
|
* or examining it might fail if we didn't clear exceptions.
|
|
*
|
|
* The error code chosen will be one of the FPE_... macros. It will be
|
|
* sent as the second argument to old BSD-style signal handlers and as
|
|
* "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
|
|
*
|
|
* XXX the FP state is not preserved across signal handlers. So signal
|
|
* handlers cannot afford to do FP unless they preserve the state or
|
|
* longjmp() out. Both preserving the state and longjmp()ing may be
|
|
* destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
|
|
* solution for signals other than SIGFPE.
|
|
*/
|
|
int
|
|
npxtrap()
|
|
{
|
|
u_short control, status;
|
|
|
|
if (!hw_float) {
|
|
printf("npxtrap: fpcurthread = %p, curthread = %p, hw_float = %d\n",
|
|
PCPU_GET(fpcurthread), curthread, hw_float);
|
|
panic("npxtrap from nowhere");
|
|
}
|
|
critical_enter();
|
|
|
|
/*
|
|
* Interrupt handling (for another interrupt) may have pushed the
|
|
* state to memory. Fetch the relevant parts of the state from
|
|
* wherever they are.
|
|
*/
|
|
if (PCPU_GET(fpcurthread) != curthread) {
|
|
control = GET_FPU_CW(curthread);
|
|
status = GET_FPU_SW(curthread);
|
|
} else {
|
|
fnstcw(&control);
|
|
fnstsw(&status);
|
|
}
|
|
|
|
if (PCPU_GET(fpcurthread) == curthread)
|
|
fnclex();
|
|
critical_exit();
|
|
return (fpetable[status & ((~control & 0x3f) | 0x40)]);
|
|
}
|
|
|
|
/*
|
|
* Implement device not available (DNA) exception
|
|
*
|
|
* It would be better to switch FP context here (if curthread != fpcurthread)
|
|
* and not necessarily for every context switch, but it is too hard to
|
|
* access foreign pcb's.
|
|
*/
|
|
|
|
static int err_count = 0;
|
|
|
|
int
|
|
npxdna(void)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
if (!hw_float)
|
|
return (0);
|
|
critical_enter();
|
|
if (PCPU_GET(fpcurthread) == curthread) {
|
|
printf("npxdna: fpcurthread == curthread %d times\n",
|
|
++err_count);
|
|
stop_emulating();
|
|
critical_exit();
|
|
return (1);
|
|
}
|
|
if (PCPU_GET(fpcurthread) != NULL) {
|
|
printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
|
|
PCPU_GET(fpcurthread),
|
|
PCPU_GET(fpcurthread)->td_proc->p_pid,
|
|
curthread, curthread->td_proc->p_pid);
|
|
panic("npxdna");
|
|
}
|
|
stop_emulating();
|
|
/*
|
|
* Record new context early in case frstor causes an IRQ13.
|
|
*/
|
|
PCPU_SET(fpcurthread, curthread);
|
|
pcb = PCPU_GET(curpcb);
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (cpu_fxsr)
|
|
fpu_clean_state();
|
|
#endif
|
|
|
|
if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
|
|
/*
|
|
* This is the first time this thread has used the FPU or
|
|
* the PCB doesn't contain a clean FPU state. Explicitly
|
|
* load an initial state.
|
|
*/
|
|
fpurstor(&npx_initialstate);
|
|
if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
|
|
fldcw(&pcb->pcb_initial_npxcw);
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
if (PCB_USER_FPU(pcb))
|
|
pcb->pcb_flags |= PCB_NPXUSERINITDONE;
|
|
} else {
|
|
/*
|
|
* The following fpurstor() may cause an IRQ13 when the
|
|
* state being restored has a pending error. The error will
|
|
* appear to have been triggered by the current (npx) user
|
|
* instruction even when that instruction is a no-wait
|
|
* instruction that should not trigger an error (e.g.,
|
|
* fnclex). On at least one 486 system all of the no-wait
|
|
* instructions are broken the same as frstor, so our
|
|
* treatment does not amplify the breakage. On at least
|
|
* one 386/Cyrix 387 system, fnclex works correctly while
|
|
* frstor and fnsave are broken, so our treatment breaks
|
|
* fnclex if it is the first FPU instruction after a context
|
|
* switch.
|
|
*/
|
|
fpurstor(pcb->pcb_save);
|
|
}
|
|
critical_exit();
|
|
|
|
return (1);
|
|
}
|
|
|
|
/*
|
|
* Wrapper for fnsave instruction, partly to handle hardware bugs. When npx
|
|
* exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
|
|
* no-wait npx instructions. See the Intel application note AP-578 for
|
|
* details. This doesn't cause any additional complications here. IRQ13's
|
|
* are inherently asynchronous unless the CPU is frozen to deliver them --
|
|
* one that started in userland may be delivered many instructions later,
|
|
* after the process has entered the kernel. It may even be delivered after
|
|
* the fnsave here completes. A spurious IRQ13 for the fnsave is handled in
|
|
* the same way as a very-late-arriving non-spurious IRQ13 from user mode:
|
|
* it is normally ignored at first because we set fpcurthread to NULL; it is
|
|
* normally retriggered in npxdna() after return to user mode.
|
|
*
|
|
* npxsave() must be called with interrupts disabled, so that it clears
|
|
* fpcurthread atomically with saving the state. We require callers to do the
|
|
* disabling, since most callers need to disable interrupts anyway to call
|
|
* npxsave() atomically with checking fpcurthread.
|
|
*
|
|
* A previous version of npxsave() went to great lengths to excecute fnsave
|
|
* with interrupts enabled in case executing it froze the CPU. This case
|
|
* can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply
|
|
* spurious freezes.
|
|
*/
|
|
void
|
|
npxsave(addr)
|
|
union savefpu *addr;
|
|
{
|
|
|
|
stop_emulating();
|
|
fpusave(addr);
|
|
|
|
start_emulating();
|
|
PCPU_SET(fpcurthread, NULL);
|
|
}
|
|
|
|
void
|
|
npxdrop()
|
|
{
|
|
struct thread *td;
|
|
|
|
/*
|
|
* Discard pending exceptions in the !cpu_fxsr case so that unmasked
|
|
* ones don't cause a panic on the next frstor.
|
|
*/
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (!cpu_fxsr)
|
|
#endif
|
|
fnclex();
|
|
|
|
td = PCPU_GET(fpcurthread);
|
|
KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
|
|
CRITICAL_ASSERT(td);
|
|
PCPU_SET(fpcurthread, NULL);
|
|
td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
start_emulating();
|
|
}
|
|
|
|
/*
|
|
* Get the state of the FPU without dropping ownership (if possible).
|
|
* It returns the FPU ownership status.
|
|
*/
|
|
int
|
|
npxgetregs(struct thread *td, union savefpu *addr)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
if (!hw_float)
|
|
return (_MC_FPOWNED_NONE);
|
|
|
|
pcb = td->td_pcb;
|
|
if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
|
|
bcopy(&npx_initialstate, addr, sizeof(npx_initialstate));
|
|
SET_FPU_CW(addr, pcb->pcb_initial_npxcw);
|
|
return (_MC_FPOWNED_NONE);
|
|
}
|
|
critical_enter();
|
|
if (td == PCPU_GET(fpcurthread)) {
|
|
fpusave(addr);
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (!cpu_fxsr)
|
|
#endif
|
|
/*
|
|
* fnsave initializes the FPU and destroys whatever
|
|
* context it contains. Make sure the FPU owner
|
|
* starts with a clean state next time.
|
|
*/
|
|
npxdrop();
|
|
critical_exit();
|
|
return (_MC_FPOWNED_FPU);
|
|
} else {
|
|
critical_exit();
|
|
bcopy(pcb->pcb_save, addr, sizeof(*addr));
|
|
return (_MC_FPOWNED_PCB);
|
|
}
|
|
}
|
|
|
|
int
|
|
npxgetuserregs(struct thread *td, union savefpu *addr)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
if (!hw_float)
|
|
return (_MC_FPOWNED_NONE);
|
|
|
|
pcb = td->td_pcb;
|
|
if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) == 0) {
|
|
bcopy(&npx_initialstate, addr, sizeof(npx_initialstate));
|
|
SET_FPU_CW(addr, pcb->pcb_initial_npxcw);
|
|
return (_MC_FPOWNED_NONE);
|
|
}
|
|
critical_enter();
|
|
if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
|
|
fpusave(addr);
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (!cpu_fxsr)
|
|
#endif
|
|
/*
|
|
* fnsave initializes the FPU and destroys whatever
|
|
* context it contains. Make sure the FPU owner
|
|
* starts with a clean state next time.
|
|
*/
|
|
npxdrop();
|
|
critical_exit();
|
|
return (_MC_FPOWNED_FPU);
|
|
} else {
|
|
critical_exit();
|
|
bcopy(&pcb->pcb_user_save, addr, sizeof(*addr));
|
|
return (_MC_FPOWNED_PCB);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set the state of the FPU.
|
|
*/
|
|
void
|
|
npxsetregs(struct thread *td, union savefpu *addr)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
if (!hw_float)
|
|
return;
|
|
|
|
pcb = td->td_pcb;
|
|
critical_enter();
|
|
if (td == PCPU_GET(fpcurthread)) {
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (!cpu_fxsr)
|
|
#endif
|
|
fnclex(); /* As in npxdrop(). */
|
|
fpurstor(addr);
|
|
critical_exit();
|
|
} else {
|
|
critical_exit();
|
|
bcopy(addr, pcb->pcb_save, sizeof(*addr));
|
|
}
|
|
if (PCB_USER_FPU(pcb))
|
|
pcb->pcb_flags |= PCB_NPXUSERINITDONE;
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
}
|
|
|
|
void
|
|
npxsetuserregs(struct thread *td, union savefpu *addr)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
if (!hw_float)
|
|
return;
|
|
|
|
pcb = td->td_pcb;
|
|
critical_enter();
|
|
if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (!cpu_fxsr)
|
|
#endif
|
|
fnclex(); /* As in npxdrop(). */
|
|
fpurstor(addr);
|
|
critical_exit();
|
|
pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
|
|
} else {
|
|
critical_exit();
|
|
bcopy(addr, &pcb->pcb_user_save, sizeof(*addr));
|
|
if (PCB_USER_FPU(pcb))
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
pcb->pcb_flags |= PCB_NPXUSERINITDONE;
|
|
}
|
|
}
|
|
|
|
static void
|
|
fpusave(addr)
|
|
union savefpu *addr;
|
|
{
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (cpu_fxsr)
|
|
fxsave(addr);
|
|
else
|
|
#endif
|
|
fnsave(addr);
|
|
}
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
/*
|
|
* On AuthenticAMD processors, the fxrstor instruction does not restore
|
|
* the x87's stored last instruction pointer, last data pointer, and last
|
|
* opcode values, except in the rare case in which the exception summary
|
|
* (ES) bit in the x87 status word is set to 1.
|
|
*
|
|
* In order to avoid leaking this information across processes, we clean
|
|
* these values by performing a dummy load before executing fxrstor().
|
|
*/
|
|
static void
|
|
fpu_clean_state(void)
|
|
{
|
|
static float dummy_variable = 0.0;
|
|
u_short status;
|
|
|
|
/*
|
|
* Clear the ES bit in the x87 status word if it is currently
|
|
* set, in order to avoid causing a fault in the upcoming load.
|
|
*/
|
|
fnstsw(&status);
|
|
if (status & 0x80)
|
|
fnclex();
|
|
|
|
/*
|
|
* Load the dummy variable into the x87 stack. This mangles
|
|
* the x87 stack, but we don't care since we're about to call
|
|
* fxrstor() anyway.
|
|
*/
|
|
__asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
|
|
}
|
|
#endif /* CPU_ENABLE_SSE */
|
|
|
|
static void
|
|
fpurstor(addr)
|
|
union savefpu *addr;
|
|
{
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
if (cpu_fxsr)
|
|
fxrstor(addr);
|
|
else
|
|
#endif
|
|
frstor(addr);
|
|
}
|
|
|
|
static device_method_t npx_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_identify, npx_identify),
|
|
DEVMETHOD(device_probe, npx_probe),
|
|
DEVMETHOD(device_attach, npx_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t npx_driver = {
|
|
"npx",
|
|
npx_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t npx_devclass;
|
|
|
|
/*
|
|
* We prefer to attach to the root nexus so that the usual case (exception 16)
|
|
* doesn't describe the processor as being `on isa'.
|
|
*/
|
|
DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
|
|
|
|
#ifdef DEV_ISA
|
|
/*
|
|
* This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
|
|
*/
|
|
static struct isa_pnp_id npxisa_ids[] = {
|
|
{ 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
npxisa_probe(device_t dev)
|
|
{
|
|
int result;
|
|
if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
|
|
device_quiet(dev);
|
|
}
|
|
return(result);
|
|
}
|
|
|
|
static int
|
|
npxisa_attach(device_t dev)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t npxisa_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, npxisa_probe),
|
|
DEVMETHOD(device_attach, npxisa_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t npxisa_driver = {
|
|
"npxisa",
|
|
npxisa_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t npxisa_devclass;
|
|
|
|
DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
|
|
#ifndef PC98
|
|
DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
|
|
#endif
|
|
#endif /* DEV_ISA */
|
|
|
|
int
|
|
fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
pcb = td->td_pcb;
|
|
KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == &pcb->pcb_user_save,
|
|
("mangled pcb_save"));
|
|
ctx->flags = 0;
|
|
if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
|
|
ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
|
|
npxexit(td);
|
|
ctx->prev = pcb->pcb_save;
|
|
pcb->pcb_save = &ctx->hwstate;
|
|
pcb->pcb_flags |= PCB_KERNNPX;
|
|
pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
pcb = td->td_pcb;
|
|
critical_enter();
|
|
if (curthread == PCPU_GET(fpcurthread))
|
|
npxdrop();
|
|
critical_exit();
|
|
pcb->pcb_save = ctx->prev;
|
|
if (pcb->pcb_save == &pcb->pcb_user_save) {
|
|
if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0)
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
else
|
|
pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
pcb->pcb_flags &= ~PCB_KERNNPX;
|
|
} else {
|
|
if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
else
|
|
pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
fpu_kern_thread(u_int flags)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
pcb = PCPU_GET(curpcb);
|
|
KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
|
|
("Only kthread may use fpu_kern_thread"));
|
|
KASSERT(pcb->pcb_save == &pcb->pcb_user_save, ("mangled pcb_save"));
|
|
KASSERT(PCB_USER_FPU(pcb), ("recursive call"));
|
|
|
|
pcb->pcb_flags |= PCB_KERNNPX;
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
is_fpu_kern_thread(u_int flags)
|
|
{
|
|
|
|
if ((curthread->td_pflags & TDP_KTHREAD) == 0)
|
|
return (0);
|
|
return ((PCPU_GET(curpcb)->pcb_flags & PCB_KERNNPX) != 0);
|
|
}
|