481 lines
12 KiB
LLVM
481 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s
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define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_bits_clear:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: blr
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%a = icmp eq i32 %P, 0
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%b = icmp eq i32 %Q, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_sign_bits_clear:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: nor 3, 3, 3
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: blr
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%a = icmp sgt i32 %P, -1
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%b = icmp sgt i32 %Q, -1
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%c = and i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @all_bits_set(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_bits_set:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 5, -1
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: xor 3, 3, 5
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: blr
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%a = icmp eq i32 %P, -1
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%b = icmp eq i32 %Q, -1
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%c = and i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_sign_bits_set:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: blr
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%a = icmp slt i32 %P, 0
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%b = icmp slt i32 %Q, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @any_bits_set(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_bits_set:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: xori 3, 3, 1
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; CHECK-NEXT: blr
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%a = icmp ne i32 %P, 0
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%b = icmp ne i32 %Q, 0
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%c = or i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_sign_bits_set:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: blr
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%a = icmp slt i32 %P, 0
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%b = icmp slt i32 %Q, 0
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%c = or i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_bits_clear:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 5, -1
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: xor 3, 3, 5
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: xori 3, 3, 1
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; CHECK-NEXT: blr
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%a = icmp ne i32 %P, -1
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%b = icmp ne i32 %Q, -1
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%c = or i1 %a, %b
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ret i1 %c
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}
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define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_sign_bits_clear:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: nor 3, 3, 3
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: blr
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%a = icmp sgt i32 %P, -1
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%b = icmp sgt i32 %Q, -1
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%c = or i1 %a, %b
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ret i1 %c
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}
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; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0
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define i32 @all_bits_clear_branch(i32* %P, i32* %Q) {
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; CHECK-LABEL: all_bits_clear_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: or. 3, 3, 4
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; CHECK-NEXT: bne 0, .LBB8_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB8_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp eq i32* %P, null
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%b = icmp eq i32* %Q, null
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%c = and i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_sign_bits_clear_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: cmpwi 0, 3, 0
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; CHECK-NEXT: blt 0, .LBB9_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB9_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp sgt i32 %P, -1
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%b = icmp sgt i32 %Q, -1
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%c = and i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define i32 @all_bits_set_branch(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_bits_set_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: cmpwi 0, 3, -1
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; CHECK-NEXT: bne 0, .LBB10_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB10_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp eq i32 %P, -1
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%b = icmp eq i32 %Q, -1
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%c = and i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) {
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; CHECK-LABEL: all_sign_bits_set_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: cmpwi 0, 3, -1
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; CHECK-NEXT: bgt 0, .LBB11_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB11_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp slt i32 %P, 0
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%b = icmp slt i32 %Q, 0
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%c = and i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0
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define i32 @any_bits_set_branch(i32* %P, i32* %Q) {
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; CHECK-LABEL: any_bits_set_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: or. 3, 3, 4
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; CHECK-NEXT: beq 0, .LBB12_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB12_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp ne i32* %P, null
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%b = icmp ne i32* %Q, null
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%c = or i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_sign_bits_set_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: cmpwi 0, 3, -1
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; CHECK-NEXT: bgt 0, .LBB13_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB13_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp slt i32 %P, 0
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%b = icmp slt i32 %Q, 0
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%c = or i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define i32 @any_bits_clear_branch(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_bits_clear_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: cmpwi 0, 3, -1
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; CHECK-NEXT: beq 0, .LBB14_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB14_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp ne i32 %P, -1
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%b = icmp ne i32 %Q, -1
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%c = or i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) {
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; CHECK-LABEL: any_sign_bits_clear_branch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: cmpwi 0, 3, 0
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; CHECK-NEXT: blt 0, .LBB15_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: li 3, 4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB15_2: # %return
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; CHECK-NEXT: li 3, 192
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; CHECK-NEXT: blr
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entry:
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%a = icmp sgt i32 %P, -1
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%b = icmp sgt i32 %Q, -1
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%c = or i1 %a, %b
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br i1 %c, label %bb1, label %return
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bb1:
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ret i32 4
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return:
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ret i32 192
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}
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define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_bits_clear_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: xxlor 34, 34, 35
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: blr
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%a = icmp eq <4 x i32> %P, zeroinitializer
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%b = icmp eq <4 x i32> %Q, zeroinitializer
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_sign_bits_clear_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxlor 34, 34, 35
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; CHECK-NEXT: vcmpgtsw 2, 2, 4
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; CHECK-NEXT: blr
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%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_bits_set_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: blr
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%a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_sign_bits_set_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: vcmpgtsw 2, 4, 2
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; CHECK-NEXT: blr
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%a = icmp slt <4 x i32> %P, zeroinitializer
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%b = icmp slt <4 x i32> %Q, zeroinitializer
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_bits_set_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: xxlor 34, 34, 35
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: xxlnor 34, 34, 34
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; CHECK-NEXT: blr
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%a = icmp ne <4 x i32> %P, zeroinitializer
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%b = icmp ne <4 x i32> %Q, zeroinitializer
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_sign_bits_set_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: xxlor 34, 34, 35
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; CHECK-NEXT: vcmpgtsw 2, 4, 2
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; CHECK-NEXT: blr
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%a = icmp slt <4 x i32> %P, zeroinitializer
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%b = icmp slt <4 x i32> %Q, zeroinitializer
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_bits_clear_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: xxlnor 34, 34, 34
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; CHECK-NEXT: blr
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%a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_sign_bits_clear_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: vcmpgtsw 2, 2, 4
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; CHECK-NEXT: blr
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%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
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; CHECK-LABEL: ne_neg1_and_ne_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi 3, 3, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: subfic 3, 3, 1
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; CHECK-NEXT: subfe 3, 4, 4
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; CHECK-NEXT: neg 3, 3
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; CHECK-NEXT: blr
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%cmp1 = icmp ne i64 %x, -1
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%cmp2 = icmp ne i64 %x, 0
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
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define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
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; CHECK-LABEL: and_eq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor 5, 5, 6
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; CHECK-NEXT: xor 3, 3, 4
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; CHECK-NEXT: or 3, 3, 5
|
|
; CHECK-NEXT: cntlzw 3, 3
|
|
; CHECK-NEXT: srwi 3, 3, 5
|
|
; CHECK-NEXT: blr
|
|
%cmp1 = icmp eq i16 %a, %b
|
|
%cmp2 = icmp eq i16 %c, %d
|
|
%and = and i1 %cmp1, %cmp2
|
|
ret i1 %and
|
|
}
|
|
|
|
define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; CHECK-LABEL: or_ne:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xor 5, 5, 6
|
|
; CHECK-NEXT: xor 3, 3, 4
|
|
; CHECK-NEXT: or 3, 3, 5
|
|
; CHECK-NEXT: cntlzw 3, 3
|
|
; CHECK-NEXT: srwi 3, 3, 5
|
|
; CHECK-NEXT: xori 3, 3, 1
|
|
; CHECK-NEXT: blr
|
|
%cmp1 = icmp ne i32 %a, %b
|
|
%cmp2 = icmp ne i32 %c, %d
|
|
%or = or i1 %cmp1, %cmp2
|
|
ret i1 %or
|
|
}
|
|
|
|
; This should not be transformed because vector compares + bitwise logic are faster.
|
|
|
|
define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
|
|
; CHECK-LABEL: and_eq_vec:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcmpequw 2, 2, 3
|
|
; CHECK-NEXT: vcmpequw 19, 4, 5
|
|
; CHECK-NEXT: xxland 34, 34, 51
|
|
; CHECK-NEXT: blr
|
|
%cmp1 = icmp eq <4 x i32> %a, %b
|
|
%cmp2 = icmp eq <4 x i32> %c, %d
|
|
%and = and <4 x i1> %cmp1, %cmp2
|
|
ret <4 x i1> %and
|
|
}
|
|
|