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o Add timeout error recovery (from a thread context to avoid the deferral of other critical interrupts). o Properly recover commands across controller reset events. o Update the driver to handle events and status codes that have been added to the MPI spec since the driver was originally written. o Make the driver more modular to improve maintainability and support dynamic "personality" registration (e.g. SCSI Initiator, RAID, SAS, FC, etc). o Shorten and simplify the common I/O path to improve driver performance. o Add RAID volume and RAID member state/settings reporting. o Add periodic volume resynchronization status reporting. o Add support for sysctl tunable resync rate, member write cache enable, and volume transaction queue depth. Sponsored by ---------------- Avid Technologies Inc: SCSI error recovery, driver re-organization, update of MPI library headers, portions of dynamic personality registration, and misc bug fixes. Wheel Open Technologies: RAID event notification, RAID member pass-thru support, firmware upload/download support, enhanced RAID resync speed, portions of dynamic personality registration, and misc bug fixes. Detailed Changes ================ mpt.c mpt_cam.c mpt_raid.c mpt_pci.c: o Add support for personality modules. Each module exports load, and unload module scope methods as well as probe, attach, event, reset, shutdown, and detach per-device instance methods mpt.c mpt.h mpt_pci.c: o The driver now associates a callback function (via an index) with every transaction submitted to the controller. This allows the main interrupt handler to absolve itself of any knowledge of individual transaction/response types by simply calling the callback function "registered" for the transaction. We use a callback index instead of a callback function pointer in each requests so we can properly handle responses (e.g. event notifications) that are not associated with a transaction. Personality modules dynamically register their callbacks with the driver core to receive the callback index to use for their handlers. o Move the interrupt handler into mpt.c. The ISR algorithm is bus transport and OS independent and thus had no reason to be in mpt_pci.c. o Simplify configuration message reply handling by copying reply frame data for the requester and storing completion status in the original request structure. o Add the mpt_complete_request_chain() helper method and use it to implement reset handlers that must abort transactions. o Keep track of all pending requests on the new requests_pending_list in the softc. o Add default handlers to mpt.c to handle generic event notifications and controller reset activities. The event handler code is largely the same as in the original driver. The reset handler is new and terminates any pending transactions with a status code indicating the controller needs to be re-initialized. o Add some endian support to the driver. A complete audit is still required for this driver to have any hope of operating in a big-endian environment. o Use inttypes.h and __inline. Come closer to being style(9) compliant. o Remove extraneous use of typedefs. o Convert request state from a strict enumeration to a series of flags. This allows us to, for example, tag transactions that have timed-out while retaining the state that the transaction is still in-flight on the controller. o Add mpt_wait_req() which allows a caller to poll or sleep for the completion of a request. Use this to simplify and factor code out from many initialization routines. We also use this to sleep for task management request completions in our CAM timeout handler. mpt.c: o Correct a bug in the event handler where request structures were freed even if the request reply was marked as a continuation reply. Continuation replies indicate that the controller still owns the request and freeing these replies prematurely corrupted controller state. o Implement firmware upload and download. On controllers that do not have dedicated NVRAM (as in the Sun v20/v40z), the firmware image is downloaded to the controller by the system BIOS. This image occupies precious controller RAM space until the host driver fetches the image, reducing the number of concurrent I/Os the controller can processes. The uploaded image is used to re-program the controller during hard reset events since the controller cannot fetch the firmware on its own. Implementing this feature allows much higher queue depths when RAID volumes are configured. o Changed configuration page accessors to allow threads to sleep rather than busy wait for completion. o Removed hard coded data transfer sizes from configuration page routines so that RAID configuration page processing is possible. mpt_reg.h: o Move controller register definitions into a separate file. mpt.h: o Re-arrange includes to allow inlined functions to be defined in mpt.h. o Add reply, event, and reset handler definitions. o Add softc fields for handling timeout and controller reset recovery. mpt_cam.c: o Move mpt_freebsd.c to mpt_cam.c. Move all core functionality, such as event handling, into mpt.c leaving only CAM SCSI support here. o Revamp completion handler to provide correct CAM status for all currently defined SCSI MPI message result codes. o Register event and reset handlers with the MPT core. Modify the event handler to notify CAM of bus reset events. The controller reset handler will abort any transactions that have timed out. All other pending CAM transactions are correctly aborted by the core driver's reset handler. o Allocate a single request up front to perform task management operations. This guarantees that we can always perform a TMF operation even when the controller is saturated with other operations. The single request also serves as a perfect mechanism of guaranteeing that only a single TMF is in flight at a time - something that is required according to the MPT Fusion documentation. o Add a helper function for issuing task management requests to the controller. This is used to abort individual requests or perform a bus reset. o Modify the CAM XPT_BUS_RESET ccb handler to wait for and properly handle the status of the bus reset task management frame used to reset the bus. The previous code assumed that the reset request would always succeed. o Add timeout recovery support. When a timeout occurs, the timed-out request is added to a queue to be processed by our recovery thread and the thread is woken up. The recovery thread processes timed-out command serially, attempting first to abort them and then falling back to a bus reset if an abort fails. o Add calls to mpt_reset() to reset the controller if any handshake command, bus reset attempt or abort attempt fails due to a timeout. o Export a secondary "bus" to CAM that exposes all volume drive members as pass-thru devices, allowing CAM to perform proper speed negotiation to hidden devices. o Add a CAM async event handler tracking the AC_FOUND_DEVICE event. Use this to trigger calls to set the per-volume queue depth once the volume is fully registered with CAM. This is required to avoid hitting firmware limits on volume queue depth. Exceeding the limit causes the firmware to hang. mpt_cam.h: o Add several helper functions for interfacing to CAM and performing timeout recovery. mpt_pci.c: o Disable interrupts on the controller before registering and enabling interrupt delivery to the OS. Otherwise we risk receiving interrupts before the driver is ready to receive them. o Make use of compatibility macros that allow the driver to be compiled under 4.x and 5.x. mpt_raid.c: o Add a per-controller instance RAID thread to perform settings changes and query status (minimizes CPU busy wait loops). o Use a shutdown handler to disable "Member Write Cache Enable" (MWCE) setting for RAID arrays set to enable MWCE During Rebuild. o Change reply handler function signature to allow handlers to defer the deletion of reply frames. Use this to allow the event reply handler to queue up events that need to be acked if no resources are available to immediately ack an event. Queued events are processed in mpt_free_request() where resources are freed. This avoids a panic on resource shortage. o Parse and print out RAID controller capabilities during driver probe. o Define, allocate, and maintain RAID data structures for volumes, hidden member physical disks and spare disks. o Add dynamic sysctls for per-instance setting of the log level, array resync rate, array member cache enable, and volume queue depth. mpt_debug.c: o Add mpt_lprt and mpt_lprtc for printing diagnostics conditioned on a particular log level to aid in tracking down driver issues. o Add mpt_decode_value() which parses the bits in an integer value based on a parsing table (mask, value, name string, tuples). mpilib/*: o Update mpi library header files to latest distribution from LSI. Submitted by: gibbs Approved by: re
464 lines
24 KiB
C
464 lines
24 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 2000-2005, LSI Logic Corporation and its contributors.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon including
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* a substantially similar Disclaimer requirement for further binary
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* redistribution.
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* 3. Neither the name of the LSI Logic Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
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* OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* Name: MPI_TARG.H
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* Title: MPI Target mode messages and structures
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* Creation Date: June 22, 2000
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*
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* MPI_TARG.H Version: 01.02.09
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*
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* Version History
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* ---------------
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*
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* Date Version Description
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* -------- -------- ------------------------------------------------------
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* 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
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* 06-06-00 01.00.01 Update version number for 1.0 release.
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* 06-22-00 01.00.02 Added _MSG_TARGET_CMD_BUFFER_POST_REPLY structure.
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* Corrected DECSRIPTOR typo to DESCRIPTOR.
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* 11-02-00 01.01.01 Original release for post 1.0 work
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* Modified target mode to use IoIndex instead of
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* HostIndex and IocIndex. Added Alias.
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* 01-09-01 01.01.02 Added defines for TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER
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* and TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER.
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* 02-20-01 01.01.03 Started using MPI_POINTER.
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* Added structures for MPI_TARGET_SCSI_SPI_CMD_BUFFER and
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* MPI_TARGET_FCP_CMD_BUFFER.
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* 03-27-01 01.01.04 Added structure offset comments.
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* 08-08-01 01.02.01 Original release for v1.2 work.
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* 09-28-01 01.02.02 Added structure for MPI_TARGET_SCSI_SPI_STATUS_IU.
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* Added PriorityReason field to some replies and
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* defined more PriorityReason codes.
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* Added some defines for to support previous version
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* of MPI.
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* 10-04-01 01.02.03 Added PriorityReason to MSG_TARGET_ERROR_REPLY.
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* 11-01-01 01.02.04 Added define for TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY.
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* 03-14-02 01.02.05 Modified MPI_TARGET_FCP_RSP_BUFFER to get the proper
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* byte ordering.
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* 05-31-02 01.02.06 Modified TARGET_MODE_REPLY_ALIAS_MASK to only include
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* one bit.
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* Added AliasIndex field to MPI_TARGET_FCP_CMD_BUFFER.
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* 09-16-02 01.02.07 Added flags for confirmed completion.
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* Added PRIORITY_REASON_TARGET_BUSY.
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* 11-15-02 01.02.08 Added AliasID field to MPI_TARGET_SCSI_SPI_CMD_BUFFER.
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* 04-01-03 01.02.09 Added OptionalOxid field to MPI_TARGET_FCP_CMD_BUFFER.
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* --------------------------------------------------------------------------
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*/
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#ifndef MPI_TARG_H
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#define MPI_TARG_H
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/******************************************************************************
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*
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* S C S I T a r g e t M e s s a g e s
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*
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*******************************************************************************/
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typedef struct _CMD_BUFFER_DESCRIPTOR
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{
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U16 IoIndex; /* 00h */
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U16 Reserved; /* 02h */
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union /* 04h */
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{
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U32 PhysicalAddress32;
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U64 PhysicalAddress64;
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} u;
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} CMD_BUFFER_DESCRIPTOR, MPI_POINTER PTR_CMD_BUFFER_DESCRIPTOR,
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CmdBufferDescriptor_t, MPI_POINTER pCmdBufferDescriptor_t;
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/****************************************************************************/
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/* Target Command Buffer Post Request */
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/****************************************************************************/
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typedef struct _MSG_TARGET_CMD_BUFFER_POST_REQUEST
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{
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U8 BufferPostFlags; /* 00h */
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U8 BufferCount; /* 01h */
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U8 ChainOffset; /* 02h */
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U8 Function; /* 03h */
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U8 BufferLength; /* 04h */
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U8 Reserved; /* 05h */
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U8 Reserved1; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */
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} MSG_TARGET_CMD_BUFFER_POST_REQUEST, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST,
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TargetCmdBufferPostRequest_t, MPI_POINTER pTargetCmdBufferPostRequest_t;
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#define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01)
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#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80)
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#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0)
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#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_64 (1)
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#define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80)
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#define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF)
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#define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */
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typedef struct _MSG_TARGET_CMD_BUFFER_POST_REPLY
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{
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U8 BufferPostFlags; /* 00h */
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U8 BufferCount; /* 01h */
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U8 MsgLength; /* 02h */
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U8 Function; /* 03h */
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U8 BufferLength; /* 04h */
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U8 Reserved; /* 05h */
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U8 Reserved1; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U16 Reserved2; /* 0Ch */
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U16 IOCStatus; /* 0Eh */
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U32 IOCLogInfo; /* 10h */
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} MSG_TARGET_CMD_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY,
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TargetCmdBufferPostReply_t, MPI_POINTER pTargetCmdBufferPostReply_t;
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/* the following structure is obsolete as of MPI v1.2 */
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typedef struct _MSG_PRIORITY_CMD_RECEIVED_REPLY
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{
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U16 Reserved; /* 00h */
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U8 MsgLength; /* 02h */
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U8 Function; /* 03h */
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U16 Reserved1; /* 04h */
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U8 Reserved2; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U8 PriorityReason; /* 0Ch */
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U8 Reserved3; /* 0Dh */
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U16 IOCStatus; /* 0Eh */
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U32 IOCLogInfo; /* 10h */
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U32 ReplyWord; /* 14h */
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} MSG_PRIORITY_CMD_RECEIVED_REPLY, MPI_POINTER PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY,
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PriorityCommandReceivedReply_t, MPI_POINTER pPriorityCommandReceivedReply_t;
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#define PRIORITY_REASON_NO_DISCONNECT (0x00)
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#define PRIORITY_REASON_SCSI_TASK_MANAGEMENT (0x01)
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#define PRIORITY_REASON_CMD_PARITY_ERR (0x02)
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#define PRIORITY_REASON_MSG_OUT_PARITY_ERR (0x03)
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#define PRIORITY_REASON_LQ_CRC_ERR (0x04)
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#define PRIORITY_REASON_CMD_CRC_ERR (0x05)
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#define PRIORITY_REASON_PROTOCOL_ERR (0x06)
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#define PRIORITY_REASON_DATA_OUT_PARITY_ERR (0x07)
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#define PRIORITY_REASON_DATA_OUT_CRC_ERR (0x08)
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#define PRIORITY_REASON_TARGET_BUSY (0x09)
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#define PRIORITY_REASON_UNKNOWN (0xFF)
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typedef struct _MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY
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{
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U16 Reserved; /* 00h */
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U8 MsgLength; /* 02h */
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U8 Function; /* 03h */
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U16 Reserved1; /* 04h */
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U8 Reserved2; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U8 PriorityReason; /* 0Ch */
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U8 Reserved3; /* 0Dh */
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U16 IOCStatus; /* 0Eh */
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U32 IOCLogInfo; /* 10h */
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U32 ReplyWord; /* 14h */
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} MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY,
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MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY,
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TargetCmdBufferPostErrorReply_t, MPI_POINTER pTargetCmdBufferPostErrorReply_t;
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typedef struct _MPI_TARGET_FCP_CMD_BUFFER
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{
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U8 FcpLun[8]; /* 00h */
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U8 FcpCntl[4]; /* 08h */
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U8 FcpCdb[16]; /* 0Ch */
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U32 FcpDl; /* 1Ch */
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U8 AliasIndex; /* 20h */
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U8 Reserved1; /* 21h */
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U16 OptionalOxid; /* 22h */
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} MPI_TARGET_FCP_CMD_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_CMD_BUFFER,
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MpiTargetFcpCmdBuffer, MPI_POINTER pMpiTargetFcpCmdBuffer;
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typedef struct _MPI_TARGET_SCSI_SPI_CMD_BUFFER
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{
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/* SPI L_Q information unit */
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U8 L_QType; /* 00h */
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U8 Reserved; /* 01h */
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U16 Tag; /* 02h */
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U8 LogicalUnitNumber[8]; /* 04h */
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U32 DataLength; /* 0Ch */
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/* SPI command information unit */
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U8 ReservedFirstByteOfCommandIU; /* 10h */
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U8 TaskAttribute; /* 11h */
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U8 TaskManagementFlags; /* 12h */
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U8 AdditionalCDBLength; /* 13h */
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U8 CDB[16]; /* 14h */
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/* Alias ID */
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U8 AliasID; /* 24h */
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U8 Reserved1; /* 25h */
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U16 Reserved2; /* 26h */
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} MPI_TARGET_SCSI_SPI_CMD_BUFFER,
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MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER,
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MpiTargetScsiSpiCmdBuffer, MPI_POINTER pMpiTargetScsiSpiCmdBuffer;
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/****************************************************************************/
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/* Target Assist Request */
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/****************************************************************************/
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typedef struct _MSG_TARGET_ASSIST_REQUEST
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{
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U8 StatusCode; /* 00h */
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U8 TargetAssistFlags; /* 01h */
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U8 ChainOffset; /* 02h */
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U8 Function; /* 03h */
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U16 QueueTag; /* 04h */
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U8 Reserved; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U32 ReplyWord; /* 0Ch */
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U8 LUN[8]; /* 10h */
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U32 RelativeOffset; /* 18h */
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U32 DataLength; /* 1Ch */
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SGE_IO_UNION SGL[1]; /* 20h */
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} MSG_TARGET_ASSIST_REQUEST, MPI_POINTER PTR_MSG_TARGET_ASSIST_REQUEST,
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TargetAssistRequest_t, MPI_POINTER pTargetAssistRequest_t;
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#define TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01)
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#define TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02)
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#define TARGET_ASSIST_FLAGS_HIGH_PRIORITY (0x04)
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#define TARGET_ASSIST_FLAGS_CONFIRMED (0x08)
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#define TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80)
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typedef struct _MSG_TARGET_ERROR_REPLY
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{
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U16 Reserved; /* 00h */
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U8 MsgLength; /* 02h */
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U8 Function; /* 03h */
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U16 Reserved1; /* 04h */
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U8 Reserved2; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U8 PriorityReason; /* 0Ch */
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U8 Reserved3; /* 0Dh */
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U16 IOCStatus; /* 0Eh */
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U32 IOCLogInfo; /* 10h */
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U32 ReplyWord; /* 14h */
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U32 TransferCount; /* 18h */
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} MSG_TARGET_ERROR_REPLY, MPI_POINTER PTR_MSG_TARGET_ERROR_REPLY,
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TargetErrorReply_t, MPI_POINTER pTargetErrorReply_t;
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/****************************************************************************/
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/* Target Status Send Request */
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/****************************************************************************/
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typedef struct _MSG_TARGET_STATUS_SEND_REQUEST
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{
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U8 StatusCode; /* 00h */
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U8 StatusFlags; /* 01h */
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U8 ChainOffset; /* 02h */
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U8 Function; /* 03h */
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U16 QueueTag; /* 04h */
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U8 Reserved; /* 06h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U32 ReplyWord; /* 0Ch */
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U8 LUN[8]; /* 10h */
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SGE_SIMPLE_UNION StatusDataSGE; /* 18h */
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} MSG_TARGET_STATUS_SEND_REQUEST, MPI_POINTER PTR_MSG_TARGET_STATUS_SEND_REQUEST,
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TargetStatusSendRequest_t, MPI_POINTER pTargetStatusSendRequest_t;
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#define TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS (0x01)
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#define TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY (0x04)
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#define TARGET_STATUS_SEND_FLAGS_CONFIRMED (0x08)
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#define TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER (0x80)
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/*
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* NOTE: FCP_RSP data is big-endian. When used on a little-endian system, this
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* structure properly orders the bytes.
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*/
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typedef struct _MPI_TARGET_FCP_RSP_BUFFER
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{
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U8 Reserved0[8]; /* 00h */
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U8 Reserved1[2]; /* 08h */
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U8 FcpFlags; /* 0Ah */
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U8 FcpStatus; /* 0Bh */
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U32 FcpResid; /* 0Ch */
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U32 FcpSenseLength; /* 10h */
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U32 FcpResponseLength; /* 14h */
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U8 FcpResponseData[8]; /* 18h */
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U8 FcpSenseData[32]; /* Pad to 64 bytes */ /* 20h */
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} MPI_TARGET_FCP_RSP_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_RSP_BUFFER,
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MpiTargetFcpRspBuffer, MPI_POINTER pMpiTargetFcpRspBuffer;
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/*
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* NOTE: The SPI status IU is big-endian. When used on a little-endian system,
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* this structure properly orders the bytes.
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*/
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typedef struct _MPI_TARGET_SCSI_SPI_STATUS_IU
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{
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U8 Reserved0; /* 00h */
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U8 Reserved1; /* 01h */
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U8 Valid; /* 02h */
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U8 Status; /* 03h */
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U32 SenseDataListLength; /* 04h */
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|
U32 PktFailuresListLength; /* 08h */
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|
U8 SenseData[52]; /* Pad the IU to 64 bytes */ /* 0Ch */
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} MPI_TARGET_SCSI_SPI_STATUS_IU, MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_STATUS_IU,
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TargetScsiSpiStatusIU_t, MPI_POINTER pTargetScsiSpiStatusIU_t;
|
|
|
|
/****************************************************************************/
|
|
/* Target Mode Abort Request */
|
|
/****************************************************************************/
|
|
|
|
typedef struct _MSG_TARGET_MODE_ABORT_REQUEST
|
|
{
|
|
U8 AbortType; /* 00h */
|
|
U8 Reserved; /* 01h */
|
|
U8 ChainOffset; /* 02h */
|
|
U8 Function; /* 03h */
|
|
U16 Reserved1; /* 04h */
|
|
U8 Reserved2; /* 06h */
|
|
U8 MsgFlags; /* 07h */
|
|
U32 MsgContext; /* 08h */
|
|
U32 ReplyWord; /* 0Ch */
|
|
U32 MsgContextToAbort; /* 10h */
|
|
} MSG_TARGET_MODE_ABORT, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT,
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|
TargetModeAbort_t, MPI_POINTER pTargetModeAbort_t;
|
|
|
|
#define TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS (0x00)
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|
#define TARGET_MODE_ABORT_TYPE_ALL_IO (0x01)
|
|
#define TARGET_MODE_ABORT_TYPE_EXACT_IO (0x02)
|
|
#define TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST (0x03)
|
|
|
|
/* Target Mode Abort Reply */
|
|
|
|
typedef struct _MSG_TARGET_MODE_ABORT_REPLY
|
|
{
|
|
U16 Reserved; /* 00h */
|
|
U8 MsgLength; /* 02h */
|
|
U8 Function; /* 03h */
|
|
U16 Reserved1; /* 04h */
|
|
U8 Reserved2; /* 06h */
|
|
U8 MsgFlags; /* 07h */
|
|
U32 MsgContext; /* 08h */
|
|
U16 Reserved3; /* 0Ch */
|
|
U16 IOCStatus; /* 0Eh */
|
|
U32 IOCLogInfo; /* 10h */
|
|
U32 AbortCount; /* 14h */
|
|
} MSG_TARGET_MODE_ABORT_REPLY, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT_REPLY,
|
|
TargetModeAbortReply_t, MPI_POINTER pTargetModeAbortReply_t;
|
|
|
|
|
|
/****************************************************************************/
|
|
/* Target Mode Context Reply */
|
|
/****************************************************************************/
|
|
|
|
#define TARGET_MODE_REPLY_IO_INDEX_MASK (0x00003FFF)
|
|
#define TARGET_MODE_REPLY_IO_INDEX_SHIFT (0)
|
|
#define TARGET_MODE_REPLY_INITIATOR_INDEX_MASK (0x03FFC000)
|
|
#define TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT (14)
|
|
#define TARGET_MODE_REPLY_ALIAS_MASK (0x04000000)
|
|
#define TARGET_MODE_REPLY_ALIAS_SHIFT (26)
|
|
#define TARGET_MODE_REPLY_PORT_MASK (0x10000000)
|
|
#define TARGET_MODE_REPLY_PORT_SHIFT (28)
|
|
|
|
|
|
#define GET_IO_INDEX(x) (((x) & TARGET_MODE_REPLY_IO_INDEX_MASK) \
|
|
>> TARGET_MODE_REPLY_IO_INDEX_SHIFT)
|
|
|
|
#define SET_IO_INDEX(t, i) \
|
|
((t) = ((t) & ~TARGET_MODE_REPLY_IO_INDEX_MASK) | \
|
|
(((i) << TARGET_MODE_REPLY_IO_INDEX_SHIFT) & \
|
|
TARGET_MODE_REPLY_IO_INDEX_MASK))
|
|
|
|
#define GET_INITIATOR_INDEX(x) (((x) & TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) \
|
|
>> TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT)
|
|
|
|
#define SET_INITIATOR_INDEX(t, ii) \
|
|
((t) = ((t) & ~TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) | \
|
|
(((ii) << TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) & \
|
|
TARGET_MODE_REPLY_INITIATOR_INDEX_MASK))
|
|
|
|
#define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \
|
|
>> TARGET_MODE_REPLY_ALIAS_SHIFT)
|
|
|
|
#define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \
|
|
(((a) << TARGET_MODE_REPLY_ALIAS_SHIFT) & \
|
|
TARGET_MODE_REPLY_ALIAS_MASK))
|
|
|
|
#define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \
|
|
>> TARGET_MODE_REPLY_PORT_SHIFT)
|
|
|
|
#define SET_PORT(t, p) ((t) = ((t) & ~TARGET_MODE_REPLY_PORT_MASK) | \
|
|
(((p) << TARGET_MODE_REPLY_PORT_SHIFT) & \
|
|
TARGET_MODE_REPLY_PORT_MASK))
|
|
|
|
/* the following obsolete values are for MPI v1.0 support */
|
|
#define TARGET_MODE_REPLY_0100_MASK_HOST_INDEX (0x000003FF)
|
|
#define TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX (0)
|
|
#define TARGET_MODE_REPLY_0100_MASK_IOC_INDEX (0x001FF800)
|
|
#define TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX (11)
|
|
#define TARGET_MODE_REPLY_0100_PORT_MASK (0x00400000)
|
|
#define TARGET_MODE_REPLY_0100_PORT_SHIFT (22)
|
|
#define TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX (0x1F800000)
|
|
#define TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX (23)
|
|
|
|
#define GET_HOST_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) \
|
|
>> TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX)
|
|
|
|
#define SET_HOST_INDEX_0100(t, hi) \
|
|
((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) | \
|
|
(((hi) << TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) & \
|
|
TARGET_MODE_REPLY_0100_MASK_HOST_INDEX))
|
|
|
|
#define GET_IOC_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) \
|
|
>> TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX)
|
|
|
|
#define SET_IOC_INDEX_0100(t, ii) \
|
|
((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) | \
|
|
(((ii) << TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) & \
|
|
TARGET_MODE_REPLY_0100_MASK_IOC_INDEX))
|
|
|
|
#define GET_INITIATOR_INDEX_0100(x) \
|
|
(((x) & TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) \
|
|
>> TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX)
|
|
|
|
#define SET_INITIATOR_INDEX_0100(t, ii) \
|
|
((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) | \
|
|
(((ii) << TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) & \
|
|
TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX))
|
|
|
|
|
|
#endif
|
|
|