Mitchell Horne 02a37049b4 riscv: zero reserved PTE bits for L2 PTEs ... As was done for L3 PTEs in r362853, mask out the reserved bits when extracting the physical address from an L2 PTE. Future versions of the spec or custom implementations may make use of these reserved bits, in which case the resulting physical address could be incorrect. Submitted by: Nathaniel Filardo <nwf20@cl.cam.ac.uk> Reviewed by: kp, mhorne Differential Revision: https://reviews.freebsd.org/D26607		2020-10-17 17:31:06 +00:00
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conf	RISC-V LINT kernel config	2020-10-09 14:45:41 +00:00
include	riscv: Add memmmap so we can mmap /dev/mem	2020-10-01 15:04:55 +00:00
riscv	riscv: zero reserved PTE bits for L2 PTEs	2020-10-17 17:31:06 +00:00
sifive	riscv/sifive: add FE310 Always-on driver	2020-04-02 00:33:15 +00:00