0fbac2a6c5
for a condition we can't handle (like the x86 longjmp). This was highlighted by attempting to build FICL into the alpha loader.
117 lines
3.5 KiB
ArmAsm
117 lines
3.5 KiB
ArmAsm
/* $NetBSD: _setjmp.S,v 1.2 1996/10/17 03:08:03 cgd Exp $ */
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/* $FreeBSD$ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <machine/asm.h>
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/*
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* C library -- _setjmp, _longjmp
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*
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* _longjmp(a,v)
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* will generate a "return(v)" from
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* the last call to
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* _setjmp(a)
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* by restoring registers from the stack,
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* The previous signal state is NOT restored.
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*/
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.set noreorder
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LEAF(_setjmp, 1)
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LDGP(pv)
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stq ra, (2 * 8)(a0) /* sc_pc = return address */
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stq s0, (( 9 + 4) * 8)(a0) /* saved bits of sc_regs */
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stq s1, ((10 + 4) * 8)(a0)
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stq s2, ((11 + 4) * 8)(a0)
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stq s3, ((12 + 4) * 8)(a0)
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stq s4, ((13 + 4) * 8)(a0)
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stq s5, ((14 + 4) * 8)(a0)
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stq s6, ((15 + 4) * 8)(a0)
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stq ra, ((26 + 4) * 8)(a0)
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stq sp, ((30 + 4) * 8)(a0)
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ldiq t0, 0xacedbadd /* sigcontext magic number */
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stq t0, ((31 + 4) * 8)(a0) /* magic in sc_regs[31] */
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/* Too bad we can't check if we actually used FP */
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ldiq t0, 1
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stq t0, (36 * 8)(a0) /* say we've used FP. */
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stt fs0, ((2 + 37) * 8)(a0) /* saved bits of sc_fpregs */
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stt fs1, ((3 + 37) * 8)(a0)
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stt fs2, ((4 + 37) * 8)(a0)
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stt fs3, ((5 + 37) * 8)(a0)
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stt fs4, ((6 + 37) * 8)(a0)
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stt fs5, ((7 + 37) * 8)(a0)
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stt fs6, ((8 + 37) * 8)(a0)
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stt fs7, ((9 + 37) * 8)(a0)
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mf_fpcr ft0 /* get FP control reg */
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stt ft0, (69 * 8)(a0) /* and store it in sc_fpcr */
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stq zero, (70 * 8)(a0) /* FP software control XXX */
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stq zero, (71 * 8)(a0) /* sc_reserved[0] */
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stq zero, (72 * 8)(a0) /* sc_reserved[1] */
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stq zero, (73 * 8)(a0) /* sc_xxx[0] */
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stq zero, (74 * 8)(a0) /* sc_xxx[1] */
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stq zero, (75 * 8)(a0) /* sc_xxx[2] */
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stq zero, (76 * 8)(a0) /* sc_xxx[3] */
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stq zero, (77 * 8)(a0) /* sc_xxx[4] */
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stq zero, (78 * 8)(a0) /* sc_xxx[5] */
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stq zero, (79 * 8)(a0) /* sc_xxx[6] */
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stq zero, (80 * 8)(a0) /* sc_xxx[7] */
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mov zero, v0 /* return zero */
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RET
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END(_setjmp)
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LEAF(_longjmp, 2)
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LDGP(pv)
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ldq ra, (2 * 8)(a0) /* sc_pc = return address */
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ldq s0, (( 9 + 4) * 8)(a0) /* saved bits of sc_regs */
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ldq s1, ((10 + 4) * 8)(a0)
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ldq s2, ((11 + 4) * 8)(a0)
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ldq s3, ((12 + 4) * 8)(a0)
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ldq s4, ((13 + 4) * 8)(a0)
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ldq s5, ((14 + 4) * 8)(a0)
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ldq s6, ((15 + 4) * 8)(a0)
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/* ldq ra, ((26 + 4) * 8)(a0) set above */
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ldq sp, ((30 + 4) * 8)(a0)
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ldt fs0, ((2 + 37) * 8)(a0) /* saved bits of sc_fpregs */
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ldt fs1, ((3 + 37) * 8)(a0)
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ldt fs2, ((4 + 37) * 8)(a0)
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ldt fs3, ((5 + 37) * 8)(a0)
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ldt fs4, ((6 + 37) * 8)(a0)
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ldt fs5, ((7 + 37) * 8)(a0)
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ldt fs6, ((8 + 37) * 8)(a0)
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ldt fs7, ((9 + 37) * 8)(a0)
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ldt ft0, (69 * 8)(a0) /* get sc_fpcr */
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mt_fpcr ft0 /* and restore it. */
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mov a1, v0 /* return second arg */
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RET
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END(_longjmp)
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