cb18f3f308
This driver works in PIO mode for now, interrupts are available only when FIFO is enabled. The FIFO cannot be used with arbitrary sizes which defeat its general use. At some point we can add DMA transfers where the FIFO can be more useful. Tested on uBMC (microBMC) and BBB. Sponsored by: Rubicon Communications (Netgate)
72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
/*-
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* Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TI_SPIVAR_H_
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#define _TI_SPIVAR_H_
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struct ti_spi_softc {
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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device_t sc_dev;
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int sc_numcs;
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struct mtx sc_mtx;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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struct {
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int cs;
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int fifolvl;
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struct spi_command *cmd;
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uint32_t len;
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uint32_t read;
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uint32_t written;
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} xfer;
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uint32_t sc_flags;
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void *sc_intrhand;
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#define sc_cs xfer.cs
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#define sc_fifolvl xfer.fifolvl
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#define sc_cmd xfer.cmd
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#define sc_len xfer.len
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#define sc_read xfer.read
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#define sc_written xfer.written
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};
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#define TI_SPI_BUSY 0x1
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#define TI_SPI_DONE 0x2
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#define TI_SPI_WRITE(_sc, _off, _val) \
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bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
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#define TI_SPI_READ(_sc, _off) \
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bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
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#define TI_SPI_LOCK(_sc) \
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mtx_lock(&(_sc)->sc_mtx)
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#define TI_SPI_UNLOCK(_sc) \
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mtx_unlock(&(_sc)->sc_mtx)
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#endif /* _TI_SPIVAR_H_ */
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