08f16287a5
Install the i386 atomic.h under /usr/include/i386 on amd64 and include when targeting i386. Reviewed by: jhb, imp
602 lines
20 KiB
C
602 lines
20 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifdef __i386__
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#include <i386/atomic.h>
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#else /* !__i386__ */
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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/*
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* To express interprocessor (as opposed to processor and device) memory
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* ordering constraints, use the atomic_*() functions with acquire and release
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* semantics rather than the *mb() functions. An architecture's memory
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* ordering (or memory consistency) model governs the order in which a
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* program's accesses to different locations may be performed by an
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* implementation of that architecture. In general, for memory regions
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* defined as writeback cacheable, the memory ordering implemented by amd64
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* processors preserves the program ordering of a load followed by a load, a
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* load followed by a store, and a store followed by a store. Only a store
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* followed by a load to a different memory location may be reordered.
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* Therefore, except for special cases, like non-temporal memory accesses or
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* memory regions defined as write combining, the memory ordering effects
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* provided by the sfence instruction in the wmb() function and the lfence
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* instruction in the rmb() function are redundant. In contrast, the
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* atomic_*() functions with acquire and release semantics do not perform
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* redundant instructions for ordinary cases of interprocessor memory
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* ordering on any architecture.
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*/
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#define mb() __asm __volatile("mfence;" : : : "memory")
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#define wmb() __asm __volatile("sfence;" : : : "memory")
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#define rmb() __asm __volatile("lfence;" : : : "memory")
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#ifdef _KERNEL
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/*
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* OFFSETOF_MONITORBUF == __pcpu_offset(pc_monitorbuf).
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*
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* The open-coded number is used instead of the symbolic expression to
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* avoid a dependency on sys/pcpu.h in machine/atomic.h consumers.
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* An assertion in amd64/vm_machdep.c ensures that the value is correct.
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*/
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#define OFFSETOF_MONITORBUF 0x100
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#endif
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#if defined(SAN_NEEDS_INTERCEPTORS) && !defined(SAN_RUNTIME)
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#include <sys/atomic_san.h>
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#else
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#include <sys/atomic_common.h>
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/*
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* Various simple operations on memory, each of which is atomic in the
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* presence of interrupts and multiple processors.
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*
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* atomic_set_char(P, V) (*(u_char *)(P) |= (V))
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* atomic_clear_char(P, V) (*(u_char *)(P) &= ~(V))
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* atomic_add_char(P, V) (*(u_char *)(P) += (V))
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* atomic_subtract_char(P, V) (*(u_char *)(P) -= (V))
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*
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* atomic_set_short(P, V) (*(u_short *)(P) |= (V))
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* atomic_clear_short(P, V) (*(u_short *)(P) &= ~(V))
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* atomic_add_short(P, V) (*(u_short *)(P) += (V))
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* atomic_subtract_short(P, V) (*(u_short *)(P) -= (V))
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*
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* atomic_set_int(P, V) (*(u_int *)(P) |= (V))
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* atomic_clear_int(P, V) (*(u_int *)(P) &= ~(V))
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* atomic_add_int(P, V) (*(u_int *)(P) += (V))
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* atomic_subtract_int(P, V) (*(u_int *)(P) -= (V))
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* atomic_swap_int(P, V) (return (*(u_int *)(P)); *(u_int *)(P) = (V);)
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* atomic_readandclear_int(P) (return (*(u_int *)(P)); *(u_int *)(P) = 0;)
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*
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* atomic_set_long(P, V) (*(u_long *)(P) |= (V))
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* atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V))
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* atomic_add_long(P, V) (*(u_long *)(P) += (V))
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* atomic_subtract_long(P, V) (*(u_long *)(P) -= (V))
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* atomic_swap_long(P, V) (return (*(u_long *)(P)); *(u_long *)(P) = (V);)
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* atomic_readandclear_long(P) (return (*(u_long *)(P)); *(u_long *)(P) = 0;)
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*/
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/*
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* Always use lock prefixes. The result is slighly less optimal for
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* UP systems, but it matters less now, and sometimes UP is emulated
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* over SMP.
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*
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* The assembly is volatilized to avoid code chunk removal by the compiler.
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* GCC aggressively reorders operations and memory clobbering is necessary
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* in order to avoid that for memory barriers.
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*/
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#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \
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static __inline void \
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atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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__asm __volatile("lock; " OP \
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: "+m" (*p) \
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: CONS (V) \
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: "cc"); \
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} \
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\
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static __inline void \
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atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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__asm __volatile("lock; " OP \
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: "+m" (*p) \
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: CONS (V) \
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: "memory", "cc"); \
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} \
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struct __hack
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/*
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* Atomic compare and set, used by the mutex functions.
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*
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* cmpset:
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* if (*dst == expect)
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* *dst = src
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*
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* fcmpset:
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* if (*dst == *expect)
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* *dst = src
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* else
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* *expect = *dst
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*
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* Returns 0 on failure, non-zero on success.
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*/
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#define ATOMIC_CMPSET(TYPE) \
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static __inline int \
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atomic_cmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE expect, u_##TYPE src) \
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{ \
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u_char res; \
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\
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__asm __volatile( \
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" lock; cmpxchg %3,%1 ; " \
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"# atomic_cmpset_" #TYPE " " \
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: "=@cce" (res), /* 0 */ \
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"+m" (*dst), /* 1 */ \
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"+a" (expect) /* 2 */ \
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: "r" (src) /* 3 */ \
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: "memory", "cc"); \
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return (res); \
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} \
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\
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static __inline int \
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atomic_fcmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE *expect, u_##TYPE src) \
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{ \
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u_char res; \
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\
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__asm __volatile( \
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" lock; cmpxchg %3,%1 ; " \
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"# atomic_fcmpset_" #TYPE " " \
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: "=@cce" (res), /* 0 */ \
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"+m" (*dst), /* 1 */ \
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"+a" (*expect) /* 2 */ \
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: "r" (src) /* 3 */ \
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: "memory", "cc"); \
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return (res); \
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}
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ATOMIC_CMPSET(char);
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ATOMIC_CMPSET(short);
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ATOMIC_CMPSET(int);
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ATOMIC_CMPSET(long);
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/*
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* Atomically add the value of v to the integer pointed to by p and return
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* the previous value of *p.
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*/
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static __inline u_int
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atomic_fetchadd_int(volatile u_int *p, u_int v)
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{
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__asm __volatile(
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" lock; xaddl %0,%1 ; "
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"# atomic_fetchadd_int"
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: "+r" (v), /* 0 */
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"+m" (*p) /* 1 */
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: : "cc");
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return (v);
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}
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/*
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* Atomically add the value of v to the long integer pointed to by p and return
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* the previous value of *p.
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*/
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static __inline u_long
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atomic_fetchadd_long(volatile u_long *p, u_long v)
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{
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__asm __volatile(
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" lock; xaddq %0,%1 ; "
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"# atomic_fetchadd_long"
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: "+r" (v), /* 0 */
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"+m" (*p) /* 1 */
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: : "cc");
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return (v);
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}
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static __inline int
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atomic_testandset_int(volatile u_int *p, u_int v)
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{
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u_char res;
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__asm __volatile(
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" lock; btsl %2,%1 ; "
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"# atomic_testandset_int"
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: "=@ccc" (res), /* 0 */
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"+m" (*p) /* 1 */
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: "Ir" (v & 0x1f) /* 2 */
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: "cc");
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return (res);
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}
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static __inline int
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atomic_testandset_long(volatile u_long *p, u_int v)
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{
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u_char res;
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__asm __volatile(
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" lock; btsq %2,%1 ; "
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"# atomic_testandset_long"
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: "=@ccc" (res), /* 0 */
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"+m" (*p) /* 1 */
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: "Jr" ((u_long)(v & 0x3f)) /* 2 */
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: "cc");
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return (res);
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}
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static __inline int
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atomic_testandclear_int(volatile u_int *p, u_int v)
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{
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u_char res;
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__asm __volatile(
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" lock; btrl %2,%1 ; "
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"# atomic_testandclear_int"
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: "=@ccc" (res), /* 0 */
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"+m" (*p) /* 1 */
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: "Ir" (v & 0x1f) /* 2 */
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: "cc");
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return (res);
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}
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static __inline int
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atomic_testandclear_long(volatile u_long *p, u_int v)
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{
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u_char res;
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__asm __volatile(
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" lock; btrq %2,%1 ; "
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"# atomic_testandclear_long"
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: "=@ccc" (res), /* 0 */
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"+m" (*p) /* 1 */
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: "Jr" ((u_long)(v & 0x3f)) /* 2 */
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: "cc");
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return (res);
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}
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/*
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* We assume that a = b will do atomic loads and stores. Due to the
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* IA32 memory model, a simple store guarantees release semantics.
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*
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* However, a load may pass a store if they are performed on distinct
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* addresses, so we need a Store/Load barrier for sequentially
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* consistent fences in SMP kernels. We use "lock addl $0,mem" for a
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* Store/Load barrier, as recommended by the AMD Software Optimization
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* Guide, and not mfence. To avoid false data dependencies, we use a
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* special address for "mem". In the kernel, we use a private per-cpu
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* cache line. In user space, we use a word in the stack's red zone
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* (-8(%rsp)).
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*/
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static __inline void
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__storeload_barrier(void)
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{
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#if defined(_KERNEL)
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__asm __volatile("lock; addl $0,%%gs:%0"
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: "+m" (*(u_int *)OFFSETOF_MONITORBUF) : : "memory", "cc");
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#else /* !_KERNEL */
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__asm __volatile("lock; addl $0,-8(%%rsp)" : : : "memory", "cc");
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#endif /* _KERNEL*/
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}
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#define ATOMIC_LOAD(TYPE) \
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static __inline u_##TYPE \
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atomic_load_acq_##TYPE(volatile u_##TYPE *p) \
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{ \
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u_##TYPE res; \
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\
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res = *p; \
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__compiler_membar(); \
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return (res); \
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} \
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struct __hack
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#define ATOMIC_STORE(TYPE) \
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static __inline void \
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atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \
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{ \
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\
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__compiler_membar(); \
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*p = v; \
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} \
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struct __hack
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static __inline void
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atomic_thread_fence_acq(void)
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{
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__compiler_membar();
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}
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static __inline void
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atomic_thread_fence_rel(void)
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{
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__compiler_membar();
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}
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static __inline void
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atomic_thread_fence_acq_rel(void)
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{
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__compiler_membar();
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}
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static __inline void
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atomic_thread_fence_seq_cst(void)
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{
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__storeload_barrier();
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}
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ATOMIC_ASM(set, char, "orb %b1,%0", "iq", v);
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ATOMIC_ASM(clear, char, "andb %b1,%0", "iq", ~v);
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ATOMIC_ASM(add, char, "addb %b1,%0", "iq", v);
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ATOMIC_ASM(subtract, char, "subb %b1,%0", "iq", v);
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ATOMIC_ASM(set, short, "orw %w1,%0", "ir", v);
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ATOMIC_ASM(clear, short, "andw %w1,%0", "ir", ~v);
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ATOMIC_ASM(add, short, "addw %w1,%0", "ir", v);
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ATOMIC_ASM(subtract, short, "subw %w1,%0", "ir", v);
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ATOMIC_ASM(set, int, "orl %1,%0", "ir", v);
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ATOMIC_ASM(clear, int, "andl %1,%0", "ir", ~v);
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ATOMIC_ASM(add, int, "addl %1,%0", "ir", v);
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ATOMIC_ASM(subtract, int, "subl %1,%0", "ir", v);
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ATOMIC_ASM(set, long, "orq %1,%0", "er", v);
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ATOMIC_ASM(clear, long, "andq %1,%0", "er", ~v);
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ATOMIC_ASM(add, long, "addq %1,%0", "er", v);
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ATOMIC_ASM(subtract, long, "subq %1,%0", "er", v);
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#define ATOMIC_LOADSTORE(TYPE) \
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ATOMIC_LOAD(TYPE); \
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ATOMIC_STORE(TYPE)
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ATOMIC_LOADSTORE(char);
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ATOMIC_LOADSTORE(short);
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ATOMIC_LOADSTORE(int);
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ATOMIC_LOADSTORE(long);
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#undef ATOMIC_ASM
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#undef ATOMIC_LOAD
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#undef ATOMIC_STORE
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#undef ATOMIC_LOADSTORE
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#ifndef WANT_FUNCTIONS
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/* Read the current value and store a new value in the destination. */
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static __inline u_int
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atomic_swap_int(volatile u_int *p, u_int v)
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{
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__asm __volatile(
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" xchgl %1,%0 ; "
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"# atomic_swap_int"
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: "+r" (v), /* 0 */
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"+m" (*p)); /* 1 */
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return (v);
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}
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static __inline u_long
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atomic_swap_long(volatile u_long *p, u_long v)
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{
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__asm __volatile(
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" xchgq %1,%0 ; "
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"# atomic_swap_long"
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: "+r" (v), /* 0 */
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"+m" (*p)); /* 1 */
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return (v);
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}
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#define atomic_set_acq_char atomic_set_barr_char
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#define atomic_set_rel_char atomic_set_barr_char
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#define atomic_clear_acq_char atomic_clear_barr_char
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#define atomic_clear_rel_char atomic_clear_barr_char
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#define atomic_add_acq_char atomic_add_barr_char
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#define atomic_add_rel_char atomic_add_barr_char
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#define atomic_subtract_acq_char atomic_subtract_barr_char
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#define atomic_subtract_rel_char atomic_subtract_barr_char
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#define atomic_cmpset_acq_char atomic_cmpset_char
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#define atomic_cmpset_rel_char atomic_cmpset_char
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#define atomic_fcmpset_acq_char atomic_fcmpset_char
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#define atomic_fcmpset_rel_char atomic_fcmpset_char
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#define atomic_set_acq_short atomic_set_barr_short
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#define atomic_set_rel_short atomic_set_barr_short
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#define atomic_clear_acq_short atomic_clear_barr_short
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#define atomic_clear_rel_short atomic_clear_barr_short
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#define atomic_add_acq_short atomic_add_barr_short
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#define atomic_add_rel_short atomic_add_barr_short
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#define atomic_subtract_acq_short atomic_subtract_barr_short
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#define atomic_subtract_rel_short atomic_subtract_barr_short
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#define atomic_cmpset_acq_short atomic_cmpset_short
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#define atomic_cmpset_rel_short atomic_cmpset_short
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#define atomic_fcmpset_acq_short atomic_fcmpset_short
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#define atomic_fcmpset_rel_short atomic_fcmpset_short
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#define atomic_set_acq_int atomic_set_barr_int
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#define atomic_set_rel_int atomic_set_barr_int
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#define atomic_clear_acq_int atomic_clear_barr_int
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#define atomic_clear_rel_int atomic_clear_barr_int
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#define atomic_add_acq_int atomic_add_barr_int
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#define atomic_add_rel_int atomic_add_barr_int
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#define atomic_subtract_acq_int atomic_subtract_barr_int
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#define atomic_subtract_rel_int atomic_subtract_barr_int
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#define atomic_cmpset_acq_int atomic_cmpset_int
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#define atomic_cmpset_rel_int atomic_cmpset_int
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#define atomic_fcmpset_acq_int atomic_fcmpset_int
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#define atomic_fcmpset_rel_int atomic_fcmpset_int
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#define atomic_set_acq_long atomic_set_barr_long
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#define atomic_set_rel_long atomic_set_barr_long
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#define atomic_clear_acq_long atomic_clear_barr_long
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#define atomic_clear_rel_long atomic_clear_barr_long
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#define atomic_add_acq_long atomic_add_barr_long
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#define atomic_add_rel_long atomic_add_barr_long
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#define atomic_subtract_acq_long atomic_subtract_barr_long
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#define atomic_subtract_rel_long atomic_subtract_barr_long
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#define atomic_cmpset_acq_long atomic_cmpset_long
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#define atomic_cmpset_rel_long atomic_cmpset_long
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#define atomic_fcmpset_acq_long atomic_fcmpset_long
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#define atomic_fcmpset_rel_long atomic_fcmpset_long
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#define atomic_readandclear_int(p) atomic_swap_int(p, 0)
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#define atomic_readandclear_long(p) atomic_swap_long(p, 0)
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#define atomic_testandset_acq_long atomic_testandset_long
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/* Operations on 8-bit bytes. */
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#define atomic_set_8 atomic_set_char
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#define atomic_set_acq_8 atomic_set_acq_char
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#define atomic_set_rel_8 atomic_set_rel_char
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#define atomic_clear_8 atomic_clear_char
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#define atomic_clear_acq_8 atomic_clear_acq_char
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#define atomic_clear_rel_8 atomic_clear_rel_char
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#define atomic_add_8 atomic_add_char
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#define atomic_add_acq_8 atomic_add_acq_char
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#define atomic_add_rel_8 atomic_add_rel_char
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#define atomic_subtract_8 atomic_subtract_char
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#define atomic_subtract_acq_8 atomic_subtract_acq_char
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#define atomic_subtract_rel_8 atomic_subtract_rel_char
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#define atomic_load_acq_8 atomic_load_acq_char
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#define atomic_store_rel_8 atomic_store_rel_char
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#define atomic_cmpset_8 atomic_cmpset_char
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#define atomic_cmpset_acq_8 atomic_cmpset_acq_char
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#define atomic_cmpset_rel_8 atomic_cmpset_rel_char
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#define atomic_fcmpset_8 atomic_fcmpset_char
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#define atomic_fcmpset_acq_8 atomic_fcmpset_acq_char
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#define atomic_fcmpset_rel_8 atomic_fcmpset_rel_char
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/* Operations on 16-bit words. */
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#define atomic_set_16 atomic_set_short
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#define atomic_set_acq_16 atomic_set_acq_short
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#define atomic_set_rel_16 atomic_set_rel_short
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#define atomic_clear_16 atomic_clear_short
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#define atomic_clear_acq_16 atomic_clear_acq_short
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#define atomic_clear_rel_16 atomic_clear_rel_short
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#define atomic_add_16 atomic_add_short
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#define atomic_add_acq_16 atomic_add_acq_short
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#define atomic_add_rel_16 atomic_add_rel_short
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#define atomic_subtract_16 atomic_subtract_short
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#define atomic_subtract_acq_16 atomic_subtract_acq_short
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#define atomic_subtract_rel_16 atomic_subtract_rel_short
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#define atomic_load_acq_16 atomic_load_acq_short
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#define atomic_store_rel_16 atomic_store_rel_short
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#define atomic_cmpset_16 atomic_cmpset_short
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#define atomic_cmpset_acq_16 atomic_cmpset_acq_short
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#define atomic_cmpset_rel_16 atomic_cmpset_rel_short
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#define atomic_fcmpset_16 atomic_fcmpset_short
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#define atomic_fcmpset_acq_16 atomic_fcmpset_acq_short
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#define atomic_fcmpset_rel_16 atomic_fcmpset_rel_short
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/* Operations on 32-bit double words. */
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#define atomic_set_32 atomic_set_int
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#define atomic_set_acq_32 atomic_set_acq_int
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#define atomic_set_rel_32 atomic_set_rel_int
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#define atomic_clear_32 atomic_clear_int
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#define atomic_clear_acq_32 atomic_clear_acq_int
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#define atomic_clear_rel_32 atomic_clear_rel_int
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#define atomic_add_32 atomic_add_int
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#define atomic_add_acq_32 atomic_add_acq_int
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#define atomic_add_rel_32 atomic_add_rel_int
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#define atomic_subtract_32 atomic_subtract_int
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#define atomic_subtract_acq_32 atomic_subtract_acq_int
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#define atomic_subtract_rel_32 atomic_subtract_rel_int
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#define atomic_load_acq_32 atomic_load_acq_int
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#define atomic_store_rel_32 atomic_store_rel_int
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#define atomic_cmpset_32 atomic_cmpset_int
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#define atomic_cmpset_acq_32 atomic_cmpset_acq_int
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#define atomic_cmpset_rel_32 atomic_cmpset_rel_int
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#define atomic_fcmpset_32 atomic_fcmpset_int
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#define atomic_fcmpset_acq_32 atomic_fcmpset_acq_int
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#define atomic_fcmpset_rel_32 atomic_fcmpset_rel_int
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#define atomic_swap_32 atomic_swap_int
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#define atomic_readandclear_32 atomic_readandclear_int
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#define atomic_fetchadd_32 atomic_fetchadd_int
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#define atomic_testandset_32 atomic_testandset_int
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#define atomic_testandclear_32 atomic_testandclear_int
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/* Operations on 64-bit quad words. */
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#define atomic_set_64 atomic_set_long
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#define atomic_set_acq_64 atomic_set_acq_long
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#define atomic_set_rel_64 atomic_set_rel_long
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#define atomic_clear_64 atomic_clear_long
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#define atomic_clear_acq_64 atomic_clear_acq_long
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#define atomic_clear_rel_64 atomic_clear_rel_long
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#define atomic_add_64 atomic_add_long
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#define atomic_add_acq_64 atomic_add_acq_long
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#define atomic_add_rel_64 atomic_add_rel_long
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#define atomic_subtract_64 atomic_subtract_long
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#define atomic_subtract_acq_64 atomic_subtract_acq_long
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#define atomic_subtract_rel_64 atomic_subtract_rel_long
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#define atomic_load_acq_64 atomic_load_acq_long
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#define atomic_store_rel_64 atomic_store_rel_long
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#define atomic_cmpset_64 atomic_cmpset_long
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#define atomic_cmpset_acq_64 atomic_cmpset_acq_long
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#define atomic_cmpset_rel_64 atomic_cmpset_rel_long
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#define atomic_fcmpset_64 atomic_fcmpset_long
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#define atomic_fcmpset_acq_64 atomic_fcmpset_acq_long
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#define atomic_fcmpset_rel_64 atomic_fcmpset_rel_long
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#define atomic_swap_64 atomic_swap_long
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#define atomic_readandclear_64 atomic_readandclear_long
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#define atomic_fetchadd_64 atomic_fetchadd_long
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#define atomic_testandset_64 atomic_testandset_long
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#define atomic_testandclear_64 atomic_testandclear_long
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/* Operations on pointers. */
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#define atomic_set_ptr atomic_set_long
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#define atomic_set_acq_ptr atomic_set_acq_long
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#define atomic_set_rel_ptr atomic_set_rel_long
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#define atomic_clear_ptr atomic_clear_long
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#define atomic_clear_acq_ptr atomic_clear_acq_long
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#define atomic_clear_rel_ptr atomic_clear_rel_long
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#define atomic_add_ptr atomic_add_long
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#define atomic_add_acq_ptr atomic_add_acq_long
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#define atomic_add_rel_ptr atomic_add_rel_long
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#define atomic_subtract_ptr atomic_subtract_long
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#define atomic_subtract_acq_ptr atomic_subtract_acq_long
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#define atomic_subtract_rel_ptr atomic_subtract_rel_long
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#define atomic_load_acq_ptr atomic_load_acq_long
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#define atomic_store_rel_ptr atomic_store_rel_long
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#define atomic_cmpset_ptr atomic_cmpset_long
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#define atomic_cmpset_acq_ptr atomic_cmpset_acq_long
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#define atomic_cmpset_rel_ptr atomic_cmpset_rel_long
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#define atomic_fcmpset_ptr atomic_fcmpset_long
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#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_long
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#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_long
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#define atomic_swap_ptr atomic_swap_long
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#define atomic_readandclear_ptr atomic_readandclear_long
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#endif /* !WANT_FUNCTIONS */
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#endif /* !SAN_NEEDS_INTERCEPTORS || SAN_RUNTIME */
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#endif /* !_MACHINE_ATOMIC_H_ */
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#endif /* __i386__ */
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